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Commit e3e1288e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx 

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (48 commits)
  DMAENGINE: move COH901318 to arch_initcall
  dma: imx-dma: fix signedness bug
  dma/timberdale: simplify conditional
  ste_dma40: remove channel_type
  ste_dma40: remove enum for endianess
  ste_dma40: remove TIM_FOR_LINK option
  ste_dma40: move mode_opt to separate config
  ste_dma40: move channel mode to a separate field
  ste_dma40: move priority to separate field
  ste_dma40: add variable to indicate valid dma_cfg
  async_tx: make async_tx channel switching opt-in
  move async raid6 test to lib/Kconfig.debug
  dmaengine: Add Freescale i.MX1/21/27 DMA driver
  intel_mid_dma: change the slave interface
  intel_mid_dma: fix the WARN_ONs
  intel_mid_dma: Add sg list support to DMA driver
  intel_mid_dma: Allow DMAC2 to share interrupt
  intel_mid_dma: Allow IRQ sharing
  intel_mid_dma: Add runtime PM support
  DMAENGINE: define a dummy filter function for ste_dma40
  ...
parents 9ae6d039 964dc256

arch/arm/mach-imx/include/mach/dma-v1.h

+2 −6
Original line number Original line Diff line number Diff line
@@ -27,6 +27,8 @@ 




#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())

#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())





#include <mach/dma.h>



#define IMX_DMA_CHANNELS  16

#define IMX_DMA_CHANNELS  16





#define DMA_MODE_READ		0

#define DMA_MODE_READ		0
@@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name); 




void imx_dma_free(int channel);

void imx_dma_free(int channel);





enum imx_dma_prio {

	DMA_PRIO_HIGH = 0,

	DMA_PRIO_MEDIUM = 1,

	DMA_PRIO_LOW = 2

};



int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);

int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);





#endif	/* __MACH_DMA_V1_H__ */
 
#endif	/* __MACH_DMA_V1_H__ */

arch/arm/mach-ux500/devices-db8500.c

+1 −12
Original line number Original line Diff line number Diff line
@@ -208,35 +208,25 @@ static struct resource dma40_resources[] = { 




/* Default configuration for physcial memcpy */

/* Default configuration for physcial memcpy */

struct stedma40_chan_cfg dma40_memcpy_conf_phy = {

struct stedma40_chan_cfg dma40_memcpy_conf_phy = {

	.channel_type = (STEDMA40_CHANNEL_IN_PHY_MODE |

	.mode = STEDMA40_MODE_PHYSICAL,

			 STEDMA40_LOW_PRIORITY_CHANNEL |

			 STEDMA40_PCHAN_BASIC_MODE),

	.dir = STEDMA40_MEM_TO_MEM,

	.dir = STEDMA40_MEM_TO_MEM,





	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.src_info.psize = STEDMA40_PSIZE_PHY_1,

	.src_info.psize = STEDMA40_PSIZE_PHY_1,

	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,

	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,





	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.psize = STEDMA40_PSIZE_PHY_1,

	.dst_info.psize = STEDMA40_PSIZE_PHY_1,

	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,

	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,

};

};

/* Default configuration for logical memcpy */

/* Default configuration for logical memcpy */

struct stedma40_chan_cfg dma40_memcpy_conf_log = {

struct stedma40_chan_cfg dma40_memcpy_conf_log = {

	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE |

			 STEDMA40_LOW_PRIORITY_CHANNEL |

			 STEDMA40_LCHAN_SRC_LOG_DST_LOG |

			 STEDMA40_NO_TIM_FOR_LINK),

	.dir = STEDMA40_MEM_TO_MEM,

	.dir = STEDMA40_MEM_TO_MEM,





	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.src_info.psize = STEDMA40_PSIZE_LOG_1,

	.src_info.psize = STEDMA40_PSIZE_LOG_1,

	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,

	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,





	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.psize = STEDMA40_PSIZE_LOG_1,

	.dst_info.psize = STEDMA40_PSIZE_LOG_1,

	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,

	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
@@ -269,7 +259,6 @@ static struct stedma40_platform_data dma40_plat_data = { 
	.memcpy_len = ARRAY_SIZE(dma40_memcpy_event),

	.memcpy_len = ARRAY_SIZE(dma40_memcpy_event),

	.memcpy_conf_phy = &dma40_memcpy_conf_phy,

	.memcpy_conf_phy = &dma40_memcpy_conf_phy,

	.memcpy_conf_log = &dma40_memcpy_conf_log,

	.memcpy_conf_log = &dma40_memcpy_conf_log,

	.llis_per_log = 8,

	.disabled_channels = {-1},

	.disabled_channels = {-1},

};

};

arch/arm/plat-mxc/include/mach/dma.h

0 → 100644
+67 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef __ASM_ARCH_MXC_DMA_H__

#define __ASM_ARCH_MXC_DMA_H__



#include <linux/scatterlist.h>

#include <linux/device.h>

#include <linux/dmaengine.h>



/*

 * This enumerates peripheral types. Used for SDMA.

 */

enum sdma_peripheral_type {

	IMX_DMATYPE_SSI,	/* MCU domain SSI */

	IMX_DMATYPE_SSI_SP,	/* Shared SSI */

	IMX_DMATYPE_MMC,	/* MMC */

	IMX_DMATYPE_SDHC,	/* SDHC */

	IMX_DMATYPE_UART,	/* MCU domain UART */

	IMX_DMATYPE_UART_SP,	/* Shared UART */

	IMX_DMATYPE_FIRI,	/* FIRI */

	IMX_DMATYPE_CSPI,	/* MCU domain CSPI */

	IMX_DMATYPE_CSPI_SP,	/* Shared CSPI */

	IMX_DMATYPE_SIM,	/* SIM */

	IMX_DMATYPE_ATA,	/* ATA */

	IMX_DMATYPE_CCM,	/* CCM */

	IMX_DMATYPE_EXT,	/* External peripheral */

	IMX_DMATYPE_MSHC,	/* Memory Stick Host Controller */

	IMX_DMATYPE_MSHC_SP,	/* Shared Memory Stick Host Controller */

	IMX_DMATYPE_DSP,	/* DSP */

	IMX_DMATYPE_MEMORY,	/* Memory */

	IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */

	IMX_DMATYPE_SPDIF,	/* SPDIF */

	IMX_DMATYPE_IPU_MEMORY,	/* IPU Memory */

	IMX_DMATYPE_ASRC,	/* ASRC */

	IMX_DMATYPE_ESAI,	/* ESAI */

};



enum imx_dma_prio {

	DMA_PRIO_HIGH = 0,

	DMA_PRIO_MEDIUM = 1,

	DMA_PRIO_LOW = 2

};



struct imx_dma_data {

	int dma_request; /* DMA request line */

	enum sdma_peripheral_type peripheral_type;

	int priority;

};



static inline int imx_dma_is_ipu(struct dma_chan *chan)

{

	return !strcmp(dev_name(chan->device->dev), "ipu-core");

}



static inline int imx_dma_is_general_purpose(struct dma_chan *chan)

{

	return !strcmp(dev_name(chan->device->dev), "imx-sdma") ||

		!strcmp(dev_name(chan->device->dev), "imx-dma");

}



#endif

arch/arm/plat-mxc/include/mach/sdma.h

0 → 100644
+17 −0
Original line number Original line Diff line number Diff line 
#ifndef __MACH_MXC_SDMA_H__

#define __MACH_MXC_SDMA_H__



/**

 * struct sdma_platform_data - platform specific data for SDMA engine

 *

 * @sdma_version	The version of this SDMA engine

 * @cpu_name		used to generate the firmware name

 * @to_version		CPU Tape out version

 */

struct sdma_platform_data {

	int sdma_version;

	char *cpu_name;

	int to_version;

};



#endif /* __MACH_MXC_SDMA_H__ */

arch/arm/plat-nomadik/include/plat/ste_dma40.h

+60 −74
Original line number Original line Diff line number Diff line 
/*

/*

 * arch/arm/plat-nomadik/include/plat/ste_dma40.h

 * Copyright (C) ST-Ericsson SA 2007-2010

 *

 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson

 * Copyright (C) ST-Ericsson 2007-2010

 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson

 * License terms: GNU General Public License (GPL) version 2

 * License terms: GNU General Public License (GPL) version 2

 * Author: Per Friden <per.friden@stericsson.com>

 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>

 */

 */
@@ -19,37 +17,20 @@ 
#define STEDMA40_DEV_DST_MEMORY (-1)

#define STEDMA40_DEV_DST_MEMORY (-1)

#define	STEDMA40_DEV_SRC_MEMORY (-1)

#define	STEDMA40_DEV_SRC_MEMORY (-1)





/*

enum stedma40_mode {

 * Description of bitfields of channel_type variable is available in

	STEDMA40_MODE_LOGICAL = 0,

 * the info structure.

	STEDMA40_MODE_PHYSICAL,

 */

	STEDMA40_MODE_OPERATION,

};





/* Priority */

enum stedma40_mode_opt {

#define STEDMA40_INFO_PRIO_TYPE_POS 2

	STEDMA40_PCHAN_BASIC_MODE = 0,

#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS)

	STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,

#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS)

	STEDMA40_PCHAN_MODULO_MODE,



	STEDMA40_PCHAN_DOUBLE_DST_MODE,

/* Mode  */

	STEDMA40_LCHAN_SRC_PHY_DST_LOG,

#define STEDMA40_INFO_CH_MODE_TYPE_POS 6

	STEDMA40_LCHAN_SRC_LOG_DST_PHY,

#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS)

};

#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)

#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)



/* Mode options */

#define STEDMA40_INFO_CH_MODE_OPT_POS 8

#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)

#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)



/* Interrupt */

#define STEDMA40_INFO_TIM_POS 10

#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)

#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)



/* End of channel_type configuration */





#define STEDMA40_ESIZE_8_BIT  0x0

#define STEDMA40_ESIZE_8_BIT  0x0

#define STEDMA40_ESIZE_16_BIT 0x1

#define STEDMA40_ESIZE_16_BIT 0x1
@@ -72,16 +53,14 @@ 
#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8

#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8

#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16

#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16





/* Maximum number of possible physical channels */

#define STEDMA40_MAX_PHYS 32



enum stedma40_flow_ctrl {

enum stedma40_flow_ctrl {

	STEDMA40_NO_FLOW_CTRL,

	STEDMA40_NO_FLOW_CTRL,

	STEDMA40_FLOW_CTRL,

	STEDMA40_FLOW_CTRL,

};

};





enum stedma40_endianess {

	STEDMA40_LITTLE_ENDIAN,

	STEDMA40_BIG_ENDIAN

};



enum stedma40_periph_data_width {

enum stedma40_periph_data_width {

	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,

	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,

	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,

	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
@@ -89,34 +68,40 @@ enum stedma40_periph_data_width { 
	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT

	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT

};

};





struct stedma40_half_channel_info {

	enum stedma40_endianess endianess;

	enum stedma40_periph_data_width data_width;

	int psize;

	enum stedma40_flow_ctrl flow_ctrl;

};



enum stedma40_xfer_dir {

enum stedma40_xfer_dir {

	STEDMA40_MEM_TO_MEM,

	STEDMA40_MEM_TO_MEM = 1,

	STEDMA40_MEM_TO_PERIPH,

	STEDMA40_MEM_TO_PERIPH,

	STEDMA40_PERIPH_TO_MEM,

	STEDMA40_PERIPH_TO_MEM,

	STEDMA40_PERIPH_TO_PERIPH

	STEDMA40_PERIPH_TO_PERIPH

};

};









/**

 * struct stedma40_chan_cfg - dst/src channel configuration

 *

 * @big_endian: true if the src/dst should be read as big endian

 * @data_width: Data width of the src/dst hardware

 * @p_size: Burst size

 * @flow_ctrl: Flow control on/off.

 */

struct stedma40_half_channel_info {

	bool big_endian;

	enum stedma40_periph_data_width data_width;

	int psize;

	enum stedma40_flow_ctrl flow_ctrl;

};



/**

/**

 * struct stedma40_chan_cfg - Structure to be filled by client drivers.

 * struct stedma40_chan_cfg - Structure to be filled by client drivers.

 *

 *

 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH

 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH

 * @channel_type: priority, mode, mode options and interrupt configuration.

 * @high_priority: true if high-priority

 * @mode: channel mode: physical, logical, or operation

 * @mode_opt: options for the chosen channel mode

 * @src_dev_type: Src device type

 * @src_dev_type: Src device type

 * @dst_dev_type: Dst device type

 * @dst_dev_type: Dst device type

 * @src_info: Parameters for dst half channel

 * @src_info: Parameters for dst half channel

 * @dst_info: Parameters for dst half channel

 * @dst_info: Parameters for dst half channel

 * @pre_transfer_data: Data to be passed on to the pre_transfer() function.

 * @pre_transfer: Callback used if needed before preparation of transfer.

 * Only called if device is set. size of bytes to transfer

 * (in case of multiple element transfer size is size of the first element).

 *

 *

 *

 *

 * This structure has to be filled by the client drivers.

 * This structure has to be filled by the client drivers.
@@ -125,15 +110,13 @@ enum stedma40_xfer_dir { 
 */

 */

struct stedma40_chan_cfg {

struct stedma40_chan_cfg {

	enum stedma40_xfer_dir			 dir;

	enum stedma40_xfer_dir			 dir;

	unsigned int				 channel_type;

	bool					 high_priority;

	enum stedma40_mode			 mode;

	enum stedma40_mode_opt			 mode_opt;

	int					 src_dev_type;

	int					 src_dev_type;

	int					 dst_dev_type;

	int					 dst_dev_type;

	struct stedma40_half_channel_info	 src_info;

	struct stedma40_half_channel_info	 src_info;

	struct stedma40_half_channel_info	 dst_info;

	struct stedma40_half_channel_info	 dst_info;

	void					*pre_transfer_data;

	int (*pre_transfer)			(struct dma_chan *chan,

						 void *data,

						 int size);

};

};





/**

/**
@@ -146,7 +129,6 @@ struct stedma40_chan_cfg { 
 * @memcpy_len: length of memcpy

 * @memcpy_len: length of memcpy

 * @memcpy_conf_phy: default configuration of physical channel memcpy

 * @memcpy_conf_phy: default configuration of physical channel memcpy

 * @memcpy_conf_log: default configuration of logical channel memcpy

 * @memcpy_conf_log: default configuration of logical channel memcpy

 * @llis_per_log: number of max linked list items per logical channel

 * @disabled_channels: A vector, ending with -1, that marks physical channels

 * @disabled_channels: A vector, ending with -1, that marks physical channels

 * that are for different reasons not available for the driver.

 * that are for different reasons not available for the driver.

 */

 */
@@ -158,23 +140,10 @@ struct stedma40_platform_data { 
	u32				 memcpy_len;

	u32				 memcpy_len;

	struct stedma40_chan_cfg	*memcpy_conf_phy;

	struct stedma40_chan_cfg	*memcpy_conf_phy;

	struct stedma40_chan_cfg	*memcpy_conf_log;

	struct stedma40_chan_cfg	*memcpy_conf_log;

	unsigned int			 llis_per_log;

	int				 disabled_channels[STEDMA40_MAX_PHYS];

	int				 disabled_channels[8];

};

};





/**

#ifdef CONFIG_STE_DMA40

 * setdma40_set_psize() - Used for changing the package size of an

 * already configured dma channel.

 *

 * @chan: dmaengine handle

 * @src_psize: new package side for src. (STEDMA40_PSIZE*)

 * @src_psize: new package side for dst. (STEDMA40_PSIZE*)

 *

 * returns 0 on ok, otherwise negative error number.

 */

int stedma40_set_psize(struct dma_chan *chan,

		       int src_psize,

		       int dst_psize);





/**

/**

 * stedma40_filter() - Provides stedma40_chan_cfg to the

 * stedma40_filter() - Provides stedma40_chan_cfg to the
@@ -237,4 +206,21 @@ dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, 
						  direction, flags);

						  direction, flags);

}

}





#else

static inline bool stedma40_filter(struct dma_chan *chan, void *data)

{

	return false;

}



static inline struct

dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,

					    dma_addr_t addr,

					    unsigned int size,

					    enum dma_data_direction direction,

					    unsigned long flags)

{

	return NULL;

}

#endif



#endif
 
#endif