Commit ddcdb1b4 authored Dec 11, 2008 by David Daney Committed by Ralf Baechle Jan 11, 2009

MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.



Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent babed555

arch/mips/include/asm/smp.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];

		#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
		#define SMP_CALL_FUNCTION 0x2
		/* Octeon - Tell another core to flush its icache */
		#define SMP_ICACHE_FLUSH 0x4


		extern void asmlinkage smp_bootstrap(void);