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Commit ddc71b24 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14"

parents b26afe6c 9fc0a9bc
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+21 −4
Original line number Diff line number Diff line
@@ -352,8 +352,8 @@ Optional properties:
				priority for realtime clients.
- qcom,sde-vbif-qos-nrt-remap:	This array is used to program vbif qos remapper register
				priority for non-realtime clients.
- qcom,sde-danger-lut:		A 4 cell property, with a format of <linear,
				tile, nrt, cwb>,
- qcom,sde-danger-lut:		Array of 5 cell property, with a format of
				<linear, tile, nrt, cwb, tile-qseed>,
				indicating the danger luts on sspp.
- qcom,sde-safe-lut-linear:	Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
@@ -363,6 +363,11 @@ Optional properties:
				<fill level, lut> in ascending fill level
				indicating the safe luts for macrotile format on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-safe-lut-macrotile-qseed: Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
				indicating the safe luts for macrotile format
				with qseed3 on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-safe-lut-nrt:	Array of 2 cell property, with a format of
				<fill level, lut> in ascending fill level
				indicating the safe luts for nrt (e.g wfd) on sspp.
@@ -379,6 +384,11 @@ Optional properties:
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for macrotile format on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-lut-macrotile-qseed: Array of 3 cell property, with a format of
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for macrotile format
				with qseed3 enabled on sspp.
				Zero fill level on the last entry identifies the default lut.
- qcom,sde-qos-lut-nrt:		Array of 3 cell property, with a format of
				<fill level, lut hi, lut lo> in ascending fill level
				indicating the qos luts for nrt (e.g wfd) on sspp.
@@ -617,8 +627,13 @@ Example:
    qcom,sde-wb-clk-ctrl = <0x2bc 16>;

    qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
            0x00000000>;
    qcom,sde-safe-lut = <0xfffc 0xff00 0xffff 0xffff>;
            0x00000000 0x0000ffff>;
    qcom,sde-safe-lut-linear = <0 0xfff8>;
    qcom,sde-safe-lut-macrotile = <0 0xf000>;
    qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>;
    qcom,sde-safe-lut-nrt = <0 0xffff>;
    qcom,sde-safe-lut-cwb = <0 0xffff>;

    qcom,sde-qos-lut-linear =
            <4 0x00000000 0x00000357>,
            <5 0x00000000 0x00003357>,
@@ -639,6 +654,8 @@ Example:
            <13 0x00002233 0x44556677>,
            <14 0x00012233 0x44556677>,
            <0 0x00112233 0x44556677>;
    qcom,sde-qos-lut-macrotile-qseed =
            <0 0x00112233 0x66777777>;
    qcom,sde-qos-lut-nrt =
            <0 0x00000000 0x00000000>;
    qcom,sde-qos-lut-cwb =
+2 −2
Original line number Diff line number Diff line
@@ -241,9 +241,9 @@ Optional properties:
- qcom,mdss-dsi-lane-2-state:		Boolean that specifies whether data lane 2 is enabled.
- qcom,mdss-dsi-lane-3-state:		Boolean that specifies whether data lane 3 is enabled.
- qcom,mdss-dsi-t-clk-post:		Specifies the byte clock cycles after mode switch.
					0x03 = default value.
					0x00 = default value.
- qcom,mdss-dsi-t-clk-pre:		Specifies the byte clock cycles before mode switch.
					0x24 = default value.
					0x00 = default value.
- qcom,mdss-dsi-stream:			Specifies the packet stream to be used.
					0 = stream 0 (default)
					1 = stream 1
+0 −34
Original line number Diff line number Diff line
@@ -400,8 +400,6 @@

/* PHY TIMINGS REVISION P */
&dsi_dual_nt35597_truly_video {
	qcom,mdss-dsi-t-clk-post = <0x17>;
	qcom,mdss-dsi-t-clk-pre = <0x18>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -414,8 +412,6 @@
};

&dsi_dual_nt35597_truly_cmd {
	qcom,mdss-dsi-t-clk-post = <0x17>;
	qcom,mdss-dsi-t-clk-pre = <0x18>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -428,8 +424,6 @@
};

&dsi_nt35597_truly_dsc_cmd {
	qcom,mdss-dsi-t-clk-post = <0x15>;
	qcom,mdss-dsi-t-clk-pre = <0x12>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
@@ -443,8 +437,6 @@
};

&dsi_nt35597_truly_dsc_video {
	qcom,mdss-dsi-t-clk-post = <0x15>;
	qcom,mdss-dsi-t-clk-pre = <0x12>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
@@ -458,8 +450,6 @@
};

&dsi_sharp_4k_dsc_video {
	qcom,mdss-dsi-t-clk-post = <0x18>;
	qcom,mdss-dsi-t-clk-pre = <0x19>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
@@ -471,8 +461,6 @@
};

&dsi_sharp_4k_dsc_cmd {
	qcom,mdss-dsi-t-clk-post = <0x18>;
	qcom,mdss-dsi-t-clk-pre = <0x19>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
@@ -484,8 +472,6 @@
};

&dsi_nt35695b_truly_fhd_video {
	qcom,mdss-dsi-t-clk-post = <0x17>;
	qcom,mdss-dsi-t-clk-pre = <0x19>;
	qcom,mdss-dsi-display-timings {
		timing@0 {
			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
@@ -497,8 +483,6 @@
};

&dsi_nt35695b_truly_fhd_cmd {
	qcom,mdss-dsi-t-clk-post = <0x17>;
	qcom,mdss-dsi-t-clk-pre = <0x19>;
	qcom,mdss-dsi-display-timings {
		timing@0 {
			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
@@ -510,8 +494,6 @@
};

&dsi_dual_sharp_1080_120hz_cmd {
	qcom,mdss-dsi-t-clk-post = <0x0f>;
	qcom,mdss-dsi-t-clk-pre = <0x36>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
@@ -524,8 +506,6 @@
};

&dsi_sharp_1080_cmd {
	qcom,mdss-dsi-t-clk-post = <0x0c>;
	qcom,mdss-dsi-t-clk-pre = <0x29>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
@@ -537,8 +517,6 @@
};

&dsi_sim_vid {
	qcom,mdss-dsi-t-clk-post = <0x15>;
	qcom,mdss-dsi-t-clk-pre = <0x12>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -551,8 +529,6 @@
};

&dsi_dual_sim_vid {
	qcom,mdss-dsi-t-clk-post = <0x15>;
	qcom,mdss-dsi-t-clk-pre = <0x12>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -565,8 +541,6 @@
};

&dsi_sim_cmd {
	qcom,mdss-dsi-t-clk-post = <0x15>;
	qcom,mdss-dsi-t-clk-pre = <0x12>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -601,8 +575,6 @@
};

&dsi_dual_sim_cmd {
	qcom,mdss-dsi-t-clk-post = <0x15>;
	qcom,mdss-dsi-t-clk-pre = <0x12>;
	qcom,mdss-dsi-display-timings {
		timing@0{
			qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
@@ -627,8 +599,6 @@
};

&dsi_sim_dsc_375_cmd {
	qcom,mdss-dsi-t-clk-post = <0x0d>;
	qcom,mdss-dsi-t-clk-pre = <0x2d>;
	qcom,mdss-dsi-display-timings {
		timing@0 { /* 1080p */
			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -648,8 +618,6 @@
};

&dsi_dual_sim_dsc_375_cmd {
	qcom,mdss-dsi-t-clk-post = <0x0d>;
	qcom,mdss-dsi-t-clk-pre = <0x2d>;
	qcom,mdss-dsi-display-timings {
		timing@0 { /* qhd */
			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -667,8 +635,6 @@
};

&dsi_sw43404_amoled_cmd {
	qcom,mdss-dsi-t-clk-post = <0x16>;
	qcom,mdss-dsi-t-clk-pre = <0x16>;
	qcom,mdss-dsi-display-timings {
		timing@0 {
			qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07
+24 −41
Original line number Diff line number Diff line
@@ -123,6 +123,11 @@
		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
						0xb0 0xc8 0xe0 0xf8 0x110>;

		qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000
						 4500000 4500000
						 4500000 4500000
						 4500000 4500000>;

		/* offsets are relative to "mdp_phys + qcom,sde-off */
		qcom,sde-sspp-clk-ctrl =
				<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
@@ -147,8 +152,8 @@
		qcom,sde-has-dest-scaler;
		qcom,sde-max-dest-scaler-input-linewidth = <2048>;
		qcom,sde-max-dest-scaler-output-linewidth = <2560>;
		qcom,sde-max-bw-low-kbps = <9600000>;
		qcom,sde-max-bw-high-kbps = <9600000>;
		qcom,sde-max-bw-low-kbps = <12800000>;
		qcom,sde-max-bw-high-kbps = <12800000>;
		qcom,sde-min-core-ib-kbps = <2400000>;
		qcom,sde-min-llcc-ib-kbps = <800000>;
		qcom,sde-min-dram-ib-kbps = <800000>;
@@ -166,44 +171,22 @@
		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

		qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
			0x00000000>;
		qcom,sde-safe-lut-linear =
			<4 0xfff8>,
			<0 0xfff0>;
		qcom,sde-safe-lut-macrotile =
			<10 0xfe00>,
			<11 0xfc00>,
			<12 0xf800>,
			<0 0xf000>;
		qcom,sde-safe-lut-nrt =
			<0 0xffff>;
		qcom,sde-safe-lut-cwb =
			<0 0xffff>;
		qcom,sde-qos-lut-linear =
			<4 0x00000000 0x00000357>,
			<5 0x00000000 0x00003357>,
			<6 0x00000000 0x00023357>,
			<7 0x00000000 0x00223357>,
			<8 0x00000000 0x02223357>,
			<9 0x00000000 0x22223357>,
			<10 0x00000002 0x22223357>,
			<11 0x00000022 0x22223357>,
			<12 0x00000222 0x22223357>,
			<13 0x00002222 0x22223357>,
			<14 0x00012222 0x22223357>,
			<0 0x00112222 0x22223357>;
		qcom,sde-qos-lut-macrotile =
			<10 0x00000003 0x44556677>,
			<11 0x00000033 0x44556677>,
			<12 0x00000233 0x44556677>,
			<13 0x00002233 0x44556677>,
			<14 0x00012233 0x44556677>,
			<0 0x00112233 0x44556677>;
		qcom,sde-qos-lut-nrt =
			<0 0x00000000 0x00000000>;
		qcom,sde-qos-lut-cwb =
			<0 0x75300000 0x00000000>;
		/* macrotile & macrotile-qseed has the same configs */
		qcom,sde-danger-lut = <0x0000000f 0x0000ffff
			0x00000000 0x00000000 0x0000ffff>;

		qcom,sde-safe-lut-linear = <0 0xfff8>;
		qcom,sde-safe-lut-macrotile = <0 0xf000>;
		/* same as safe-lut-macrotile */
		qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>;
		qcom,sde-safe-lut-nrt = <0 0xffff>;
		qcom,sde-safe-lut-cwb = <0 0xffff>;

		qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>;
		qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
		qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
		qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
		qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>;

		qcom,sde-cdp-setting = <1 1>, <1 0>;

@@ -441,7 +424,7 @@
		qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233
							0x44556677 0x00112233>;
		qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>;
		qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>;
		qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000f000>;

		qcom,mdss-default-ot-rd-limit = <32>;
		qcom,mdss-default-ot-wr-limit = <32>;
+13 −0
Original line number Diff line number Diff line
@@ -254,6 +254,7 @@ static inline int pll_reg_read(void *context, unsigned int reg,
					unsigned int *val)
{
	int rc = 0;
	u32 data;
	struct mdss_pll_resources *rsc = context;

	rc = mdss_pll_resource_enable(rsc, true);
@@ -262,7 +263,19 @@ static inline int pll_reg_read(void *context, unsigned int reg,
		return rc;
	}

	/*
	 * DSI PHY/PLL should be both powered on when reading PLL
	 * registers. Since PHY power has been enabled in DSI PHY
	 * driver, only PLL power is needed to enable here.
	 */
	data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0);
	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data | BIT(5));
	ndelay(250);

	*val = MDSS_PLL_REG_R(rsc->pll_base, reg);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data);

	(void)mdss_pll_resource_enable(rsc, false);

	return rc;
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