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Commit dd990aca authored by Veera Sundaram Sankaran's avatar Veera Sundaram Sankaran
Browse files

drm/msm/sde: issue LUTDMA kickoff based on ctl paths 



Currently LUTDMA kickoff is triggered based on the
number of physical encoders. This might cause redundant
LUTDMA kickoffs as the physical encoders  might be driven
by a single ctl. Move this in-line with the CTL flush logic
which issues the flush based on the number of CTL paths.

Change-Id: Icc1b8cafaaa3d713a490474d72c1298ecbd02c54
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent f023ee64

drivers/gpu/drm/msm/sde/sde_encoder.c

+10 −12
Original line number Diff line number Diff line
@@ -3655,15 +3655,9 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) 
		if (!ctl)

			continue;



		/* make reg dma kickoff as blocking for vidoe-mode */

		if (phys->hw_ctl->ops.reg_dma_flush)

			phys->hw_ctl->ops.reg_dma_flush(phys->hw_ctl,

					is_vid_mode);



		if (phys->connector)

			topology = sde_connector_get_topology_name(

					phys->connector);



		/*

		 * don't wait on ppsplit slaves or skipped encoders because

		 * they dont receive irqs
@@ -3674,17 +3668,21 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) 
			set_bit(i, sde_enc->frame_busy_mask);



		if (!phys->ops.needs_single_flush ||

				!phys->ops.needs_single_flush(phys))

				!phys->ops.needs_single_flush(phys)) {

			if (ctl->ops.reg_dma_flush)

				ctl->ops.reg_dma_flush(ctl, is_vid_mode);

			_sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);

		else if (ctl->ops.get_pending_flush)

		} else if (ctl->ops.get_pending_flush) {

			ctl->ops.get_pending_flush(ctl, &pending_flush);

		}

	}



	/* for split flush, combine pending flush masks and send to master */

	if (pending_flush.pending_flush_mask && sde_enc->cur_master) {

		_sde_encoder_trigger_flush(

				&sde_enc->base,

				sde_enc->cur_master,

		ctl = sde_enc->cur_master->hw_ctl;

		if (ctl->ops.reg_dma_flush)

			ctl->ops.reg_dma_flush(ctl, is_vid_mode);

		_sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,

						&pending_flush);

	}