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Commit dd17d836 authored by Ramachandran Venkataramani's avatar Ramachandran Venkataramani
Browse files

ARM: dts: msm: Add SDE DP support on SA8195 



Add the device nodes required to enable support for
native display port on SA8195.

Change-Id: I0779dd95df24023be9ab2f4a9e1192caed3edf19
Signed-off-by: default avatarRamachandran Venkataramani <ramavenk@codeaurora.org>
parent 9fcd72d5

arch/arm64/boot/dts/qcom/sdmshrike-sde-pll.dtsi

+25 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -65,4 +65,28 @@ 
		};

	};



	mdss_dp_pll: qcom,mdss_dp_pll@88ea000 {

		compatible = "qcom,mdss_dp_pll_7nm";

		label = "MDSS DP PLL";

		cell-index = <0>;

		#clock-cells = <1>;



		reg = <0x88ea000 0x200>,

		      <0x88eaa00 0x200>,

		      <0x88ea200 0x200>,

		      <0x88ea600 0x200>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk", "pipe_clk";

		clock-rate = <0>;

	};



};

arch/arm64/boot/dts/qcom/sdmshrike-sde.dtsi

+114 −5
Original line number Diff line number Diff line
@@ -14,9 +14,9 @@ 
&soc {

	mdss_mdp: qcom,mdss_mdp@ae00000 {

		compatible = "qcom,sde-kms";

		reg = <0x0ae00000 0x84208>,

		      <0x0aeb0000 0x2008>,

		      <0x0aeac000 0x214>;

		reg = <0xae00000 0x84208>,

		      <0xaeb0000 0x2008>,

		      <0xaeac000 0x214>;

		reg-names = "mdp_phys",

			"vbif_phys",

			"regdma_phys";
@@ -394,8 +394,8 @@ 


	mdss_rotator: qcom,mdss_rotator@ae00000 {

		compatible = "qcom,sde_rotator";

		reg = <0x0ae00000 0xac000>,

		      <0x0aeb8000 0x3000>;

		reg = <0xae00000 0xac000>,

		      <0xaeb8000 0x3000>;

		reg-names = "mdp_phys",

			"rot_vbif_phys";
@@ -605,4 +605,113 @@ 
			};

		};

	};



	sde_dp: qcom,dp_display@0{

		cell-index = <0>;

		compatible = "qcom,dp-display";



		reg = <0xae90000 0x0dc>,

			<0xae90200 0x0c0>,

			<0xae90400 0x508>,

			<0xae90a00 0x094>,

			<0x88eaa00 0x200>,

			<0x88ea200 0x200>,

			<0x88ea600 0x200>,

			<0xaf02000 0x1a0>,

			<0x780000 0x621c>,

			<0x88ea040 0x10>,

			<0x88e8000 0x20>,

			<0xaee1000 0x034>,

			<0xae91000 0x094>;

		/* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */

		reg-names = "dp_ahb", "dp_aux", "dp_link",

			"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

			"dp_mmss_cc", "qfprom_physical", "dp_pll",

			"usb3_dp_com", "hdcp_physical", "dp_p1";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <12 0>;



		clocks =  <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;

		clock-names = "core_aux_clk", "core_usb_ref_clk_src",

			"core_usb_ref_clk", "core_usb_pipe_clk",

			"link_clk", "link_iface_clk",

			"crypto_clk", "pixel_clk_rcg", "pixel_parent",

			"pixel1_clk_rcg", "pixel1_parent",

			"strm0_pixel_clk", "strm1_pixel_clk";



		qcom,phy-version = <0x420>;

		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 13];

		qcom,aux-cfg2-settings = [28 24];

		qcom,aux-cfg3-settings = [2c 00];

		qcom,aux-cfg4-settings = [30 0a];

		qcom,aux-cfg5-settings = [34 26];

		qcom,aux-cfg6-settings = [38 0a];

		qcom,aux-cfg7-settings = [3c 03];

		qcom,aux-cfg8-settings = [40 b7];

		qcom,aux-cfg9-settings = [44 03];



		qcom,max-pclk-frequency-khz = <675000>;



		qcom,mst-enable;

		qcom,dsc-feature-enable;

		qcom,fec-feature-enable;

		qcom,max-dp-dsc-blks = <2>;

		qcom,max-dp-dsc-input-width-pixs = <2048>;



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};

};