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Commit dc1050aa authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: sm6150: Add support for enabling the critical clocks"

parents 80e78e2b 0c420cea

drivers/clk/qcom/common.c

+20 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2014, 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2014, 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -346,4 +346,23 @@ int qcom_cc_register_rcg_dfs(struct platform_device *pdev, 
}

EXPORT_SYMBOL(qcom_cc_register_rcg_dfs);



int qcom_cc_enable_critical_clks(const struct qcom_cc_critical_desc *desc)

{

	struct clk_regmap **clkr = desc->clks;

	size_t num_clks = desc->num_clks;

	int i, ret = 0;



	for (i = 0; i < num_clks; i++) {

		ret = clk_enable_regmap(&(clkr[i]->hw));

		if (ret) {

			pr_err("Failed to enable %s\n",

					clk_hw_get_name(&(clkr[i]->hw)));

			break;

		}

	}



	return ret;

}

EXPORT_SYMBOL(qcom_cc_enable_critical_clks);



MODULE_LICENSE("GPL v2");

drivers/clk/qcom/common.h

+8 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014, 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014, 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -61,6 +61,11 @@ struct qcom_cc_dfs_desc { 
	size_t num_clks;

};



struct qcom_cc_critical_desc {

	struct clk_regmap **clks;

	size_t num_clks;

};



extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,

					     unsigned long rate);

extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
@@ -84,4 +89,6 @@ extern int qcom_cc_probe(struct platform_device *pdev, 
extern const struct clk_ops clk_dummy_ops;

extern int qcom_cc_register_rcg_dfs(struct platform_device *pdev,

			 const struct qcom_cc_dfs_desc *desc);

extern int qcom_cc_enable_critical_clks(

		const struct qcom_cc_critical_desc *desc);

#endif

drivers/clk/qcom/gcc-sm6150.c

+29 −0
Original line number Diff line number Diff line
@@ -3597,6 +3597,24 @@ static struct clk_dfs gcc_dfs_clocks[] = { 
	{ &gcc_qupv3_wrap1_s5_clk_src, DFS_ENABLE_RCG },

};



static struct clk_regmap *gcc_sm6150_critical_clocks[] = {

	&gcc_camera_ahb_clk.clkr,

	&gcc_camera_xo_clk.clkr,

	&gcc_cpuss_ahb_clk.clkr,

	&gcc_cpuss_gnoc_clk.clkr,

	&gcc_disp_ahb_clk.clkr,

	&gcc_disp_xo_clk.clkr,

	&gcc_gpu_cfg_ahb_clk.clkr,

	&gcc_sys_noc_cpuss_ahb_clk.clkr,

	&gcc_video_ahb_clk.clkr,

	&gcc_video_xo_clk.clkr

};



static const struct qcom_cc_critical_desc gcc_sm6150_critical_desc = {

	.clks = gcc_sm6150_critical_clocks,

	.num_clks = ARRAY_SIZE(gcc_sm6150_critical_clocks),

};



static const struct qcom_cc_dfs_desc gcc_sm6150_dfs_desc = {

	.clks = gcc_dfs_clocks,

	.num_clks = ARRAY_SIZE(gcc_dfs_clocks),
@@ -3627,12 +3645,23 @@ static const struct of_device_id gcc_sm6150_match_table[] = { 
};

MODULE_DEVICE_TABLE(of, gcc_sm6150_match_table);



static int gcc_sa6150_resume(struct device *dev)

{

	return qcom_cc_enable_critical_clks(&gcc_sm6150_critical_desc);

}



static const struct dev_pm_ops gcc_sa6150_pm_ops = {

	.restore_early = gcc_sa6150_resume,

};



static void gcc_sm6150_fixup_sa6155(struct platform_device *pdev)

{

	vdd_cx.num_levels = VDD_NUM_SA6155;

	vdd_cx.cur_level = VDD_NUM_SA6155;

	vdd_cx_ao.num_levels = VDD_NUM_SA6155;

	vdd_cx_ao.cur_level = VDD_NUM_SA6155;



	pdev->dev.driver->pm =  &gcc_sa6150_pm_ops;

}



static int gcc_sm6150_probe(struct platform_device *pdev)

drivers/clk/qcom/gpucc-sm6150.c

+10 −1
Original line number Diff line number Diff line
@@ -508,6 +508,15 @@ static const struct qcom_cc_desc gpu_cc_sm6150_desc = { 
	.num_hwclks = ARRAY_SIZE(gpu_cc_sm6150_hws),

};



static struct clk_regmap *gpu_cc_sm6150_critical_clocks[] = {

	&gpu_cc_ahb_clk.clkr,

};



static const struct qcom_cc_critical_desc gpu_cc_sm6150_critical_desc = {

	.clks = gpu_cc_sm6150_critical_clocks,

	.num_clks = ARRAY_SIZE(gpu_cc_sm6150_critical_clocks),

};



static const struct of_device_id gpu_cc_sm6150_match_table[] = {

	{ .compatible = "qcom,gpucc-sm6150" },

	{ .compatible = "qcom,gpucc-sa6155" },
@@ -541,7 +550,7 @@ static int gpu_cc_sm6150_resume(struct device *dev) 


	gpu_cc_sm6150_configure(regmap);



	return 0;

	return qcom_cc_enable_critical_clks(&gpu_cc_sm6150_critical_desc);

}



static const struct dev_pm_ops gpu_cc_sm6150_pm_ops = {

drivers/clk/qcom/videocc-sm6150.c

+21 −0
Original line number Diff line number Diff line
@@ -326,6 +326,15 @@ static const struct qcom_cc_desc video_cc_sm6150_desc = { 
	.num_clks = ARRAY_SIZE(video_cc_sm6150_clocks),

};



static struct clk_regmap *video_cc_sm6150_critical_clocks[] = {

	&video_cc_xo_clk.clkr,

};



static const struct qcom_cc_critical_desc video_cc_sm6150_critical_desc = {

	.clks = video_cc_sm6150_critical_clocks,

	.num_clks = ARRAY_SIZE(video_cc_sm6150_critical_clocks),

};



static const struct of_device_id video_cc_sm6150_match_table[] = {

	{ .compatible = "qcom,videocc-sm6150" },

	{ .compatible = "qcom,videocc-sa6155" },
@@ -333,10 +342,22 @@ static const struct of_device_id video_cc_sm6150_match_table[] = { 
};

MODULE_DEVICE_TABLE(of, video_cc_sm6150_match_table);



static int video_cc_sa6150_resume(struct device *dev)

{

	return qcom_cc_enable_critical_clks(&video_cc_sm6150_critical_desc);

}



static const struct dev_pm_ops video_cc_sa6150_pm_ops = {

	.restore_early = video_cc_sa6150_resume,

};





static void videocc_sm6150_fixup_sa6155(struct platform_device *pdev)

{

	vdd_cx.num_levels = VDD_NUM_SA6155;

	vdd_cx.cur_level = VDD_NUM_SA6155;



	pdev->dev.driver->pm =  &video_cc_sa6150_pm_ops;

}



static int video_cc_sm6150_probe(struct platform_device *pdev)