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Commit d832c37f authored by Steve Cohen's avatar Steve Cohen
Browse files

drm/msm/sde: Fix disabling of Merge3D block 



Fix disabling of Merge3D during a seamless mode switch.  When
switching from Merge3D to DSC merge, the register programming
to disable Merge3D must be flushed in the same vsync as the DSC
enable.  Also ensure Merge3D ops are populated only for HW that
supports this feature.

Change-Id: I0c4ae477db1b0d651cc35ae6cc70548eb9a474e6
Signed-off-by: default avatarSteve Cohen <cohens@codeaurora.org>
parent 8b8c7dbc

drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c

+2 −8
Original line number Diff line number Diff line
@@ -131,7 +131,6 @@ static void _sde_encoder_phys_cmd_update_flush_mask( 
{

	struct sde_encoder_phys_cmd *cmd_enc;

	struct sde_hw_ctl *ctl;

	bool merge_3d_enable = false;



	if (!phys_enc || !phys_enc->hw_intf || !phys_enc->hw_pp)

		return;
@@ -149,16 +148,11 @@ static void _sde_encoder_phys_cmd_update_flush_mask( 
		return;

	}



	if (sde_encoder_helper_get_3d_blend_mode(phys_enc) != BLEND_3D_NONE)

		merge_3d_enable = true;



	ctl->ops.update_bitmask_intf(ctl, phys_enc->intf_idx, 1);





	if (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&

			phys_enc->hw_pp->merge_3d)

	if (ctl->ops.update_bitmask_merge3d && phys_enc->hw_pp->merge_3d)

		ctl->ops.update_bitmask_merge3d(ctl,

			phys_enc->hw_pp->merge_3d->idx, merge_3d_enable);

			phys_enc->hw_pp->merge_3d->idx, 1);



	SDE_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d intf_idx %x\n",

			ctl->idx - CTL_0, phys_enc->intf_idx);

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+2 −7
Original line number Diff line number Diff line
@@ -785,7 +785,6 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
	struct sde_encoder_phys_vid *vid_enc;

	struct sde_hw_intf *intf;

	struct sde_hw_ctl *ctl;

	bool merge_3d_enable = false;



	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||

			!phys_enc->parent->dev->dev_private ||
@@ -846,15 +845,11 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 
		goto skip_flush;

	}



	if (sde_encoder_helper_get_3d_blend_mode(phys_enc) != BLEND_3D_NONE)

		merge_3d_enable = true;



	ctl->ops.update_bitmask_intf(ctl, intf->idx, 1);



	if (test_bit(SDE_CTL_ACTIVE_CFG, &ctl->caps->features) &&

			phys_enc->hw_pp->merge_3d)

	if (ctl->ops.update_bitmask_merge3d && phys_enc->hw_pp->merge_3d)

		ctl->ops.update_bitmask_merge3d(ctl,

			phys_enc->hw_pp->merge_3d->idx, merge_3d_enable);

			phys_enc->hw_pp->merge_3d->idx, 1);



skip_flush:

	SDE_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d intf %d\n",

drivers/gpu/drm/msm/sde/sde_hw_pingpong.c

+2 −1
Original line number Diff line number Diff line
@@ -495,9 +495,10 @@ static void _setup_pingpong_ops(struct sde_hw_pingpong_ops *ops, 
		ops->setup_dither = NULL;

		break;

	}

	if (test_bit(SDE_PINGPONG_MERGE_3D, &hw_cap->features))

	if (test_bit(SDE_PINGPONG_MERGE_3D, &hw_cap->features)) {

		ops->setup_3d_mode = sde_hw_pp_setup_3d_merge_mode;

		ops->reset_3d_mode = sde_hw_pp_reset_3d_merge_mode;

	}

};



static struct sde_hw_blk_ops sde_hw_ops = {