Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14"

- qcom,mdss-dsi-color-order:		Specifies the R, G and B channel ordering.

					"rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value)

					"rgb_swap_rbg" = DSI_RGB_SWAP_RBG

					"rgb_swap_bgr" = DSI_RGB_SWAP_BGR

					"rgb_swap_brg" = DSI_RGB_SWAP_BRG

					"rgb_swap_grb" = DSI_RGB_SWAP_GRB

					"rgb_swap_gbr" = DSI_RGB_SWAP_GBR

					frequencies in Hz for the given panel.

- qcom,dsi-dyn-clk-skip-timing-update:	Boolean to specify whether to skip phy timing parameter

					update during dynamic clock switch.

- qcom,csi-proxy-enable:		Boolean to config DSI transmission packet DataTypes to simulate the CSI-2 compatible signal

Required properties for sub-nodes:	None

Optional properties:

- clock-names:          Names of the clocks corresponding to handles. Following clocks are required:

			"core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk",

			"core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk",

			"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent".

			"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent", "bond_pixel_parent".

			Only under multiple DPs pixel clock bonding mode, i.e. triple DPs bonding, bond_pixel_parent

			is used, replacing the pixel_parent for single DP mode.

- gdsc-supply:		phandle to gdsc regulator node.

- vdda-1p2-supply:		phandle to vdda 1.2V regulator node.

- vdda-0p9-supply:		phandle to vdda 0.9V regulator node.

display interfaces, e.g. Display Port, and the audio subsystem.

Optional properties:

- qcom,intf-index:		u32 integer array to specify the intf instances

- qcom,phy-index:		u32 integer to specify the phy instance

- qcom,ext-disp:		phandle for msm-ext-display module

- compatible:			Must be "qcom,msm-ext-disp"

- qcom,dp-low-power-hw-hpd:	Low power hardware HPD feature enable control node

- qcom,phy-version:		Phy version

- qcom,phy-mode:		Phy mode from the following list. If not specified, the default PHY mode is decided by the PHY driver,

				which is "dp" for DP/USB combo PHY, "edp" for eDP/DP combo PHY

				"dp" - DP PHY mode

				"minidp" - MiniDP PHY mode

				"edp" - eDP PHY mode

				"edp-highswing" - eDP PHY mode, high swing/pre-emphasis

- qcom,pn-swap-lane-map:	P/N swap configuration of each lane

- pinctrl-names:		List of names to assign mdss pin states defined in pinctrl device node

				Refer to pinctrl-bindings.txt

- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one

- qcom,dp-aux-bridge:		phandle for dp aux bridge module, for 3rd party dp bridge only.

- qcom,dp-aux-bridge-sim:	phandle for dp aux bridge module, for internal mst debug simulation only.

- qcom,dp-force-bond-mode:	Ignore tile information from EDID and force DP to work in bond mode.

- qcom,bond-dual-ctrl:		u32 array to specify the cell-index of the two DP controllers that support bond mode.

				The first controller in the array is the bond master. Driver will switch to bond mode

				if both DP controllers are connected to the same dual DP input monitor.

				e.g. <1, 0> will bond DP0 and DP1, and DP1 is the master, and DP0 is the salve.

- qcom,bond-tri-ctrl:		u32 array to specify the cell-index of the three DP controllers that support bond mode.

				The first controller in the array is the bond master. Driver will switch to bond mode

				if all three DP controllers are connected to the same triple DP input monitor.

				e.g. <2, 0, 1> will bond DP0, DP1 and DP2 together, and DP2 is the master, DP0/DP1 are the slaves.

[Optional child nodes]: These nodes are for devices which are

dependent on msm_ext_disp. If msm_ext_disp is disabled then

			"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm",

			"qcom,mdss_dp_pll_14nm", "qcom,mdss_hdmi_pll_28lpm",

			"qcom,mdss_dsi_pll_7nm_v2", "qcom,mdss_dp_pll_sdm660",

			"qcom,mdss_dsi_pll_sdm660", "qcom,mdss_dsi_pll_12nm"

			"qcom,mdss_dsi_pll_sdm660", "qcom,mdss_dsi_pll_12nm",

			"qcom,mdss_edp_pll_7nm"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

		qcom,sde-qdss-off = <0x81a00>;

		qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>;

		qcom,sde-dither-off = <0x30e0 0x30e0>;

		qcom,sde-dither-version = <0x00010000>;

		qcom,sde-dither-size = <0x20>;

/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

};

static struct clk_fixed_factor dp_phy_pll_link_clk = {

#ifdef CONFIG_FB_MSM_MDSS

	.div = 5,

#else

	.div = 10,

#endif

	.mult = 1,

	.hw.init = &(struct clk_init_data){

	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX1_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);

	if (pdb->orientation == ORIENTATION_CC2)

	if (pdb->orientation == ORIENTATION_CC2) {

		if (dp_res->target_id == MDSS_PLL_TARGET_SDM660)

			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc8);

		else

			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc9);

	} else {

		if (dp_res->target_id == MDSS_PLL_TARGET_SDM660)

			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd8);

		else

			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd9);

	}

	wmb(); /* make sure write happens */

	/* TX Lane configuration */