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Commit cfca7b85 authored by Jinesh K. Jayakumar's avatar Jinesh K. Jayakumar
Browse files

net: aquantia: support for 32-bit ARM target



Add support to build the Aquantia forwarding driver for 32-bit
ARM target.

CRs-Fixed: 2309519
Change-Id: I4e0596a23fe96f81db12260b210d5cfd6e56b205
Signed-off-by: default avatarJinesh K. Jayakumar <jineshk@codeaurora.org>
parent 8439d074
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+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ config AQTION

config AQFWD
	tristate "aQuantia Forwarding driver"
	depends on PCI && (X86_64 || ARM64)
	depends on PCI && (X86_64 || ARM64 || ARM)
	---help---
	  This enables the support for forwarding driver for the aQuantia AQtion(tm) Ethernet card.

+2 −2
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ static void atl_fwd_init_ring(struct atl_fwd_ring *fwd_ring)
	int lxo_bit = !!(flags & ATL_FWR_LXO);

	atl_write(hw, ATL_RING_BASE_LSW(ring), ring->daddr);
	atl_write(hw, ATL_RING_BASE_MSW(ring), ring->daddr >> 32);
	atl_write(hw, ATL_RING_BASE_MSW(ring), (u64)ring->daddr >> 32);

	if (dir_tx) {
		atl_write(hw, ATL_TX_RING_THRESH(ring),
@@ -511,7 +511,7 @@ int atl_fwd_request_event(struct atl_fwd_event *evt)
		atl_write(hw, ATL_TX_RING_HEAD_WB_LSW(hwring),
			evt->tx_head_wrb);
		atl_write(hw, ATL_TX_RING_HEAD_WB_MSW(hwring),
			evt->tx_head_wrb >> 32);
			(u64)evt->tx_head_wrb >> 32);
		return 0;
	}

+2 −2
Original line number Diff line number Diff line
@@ -1492,7 +1492,7 @@ static void atl_start_rx_ring(struct atl_desc_ring *ring)
	unsigned int rx_ctl;

	atl_write(hw, ATL_RING_BASE_LSW(ring), ring->hw.daddr);
	atl_write(hw, ATL_RING_BASE_MSW(ring), ring->hw.daddr >> 32);
	atl_write(hw, ATL_RING_BASE_MSW(ring), (u64)ring->hw.daddr >> 32);

	atl_write(hw, ATL_RX_RING_TAIL(ring), ring->tail);
	atl_write(hw, ATL_RX_RING_BUF_SIZE(ring),
@@ -1515,7 +1515,7 @@ static void atl_start_tx_ring(struct atl_desc_ring *ring)
	struct atl_hw *hw = &nic->hw;

	atl_write(hw, ATL_RING_BASE_LSW(ring), ring->hw.daddr);
	atl_write(hw, ATL_RING_BASE_MSW(ring), ring->hw.daddr >> 32);
	atl_write(hw, ATL_RING_BASE_MSW(ring), (u64)ring->hw.daddr >> 32);

	/* Enable TSO on all active Tx rings */
	atl_write(hw, ATL_TX_LSO_CTRL, BIT(nic->nvecs) - 1);