Loading arch/arm64/boot/dts/qcom/sa8155-adp-alcor.dtsi +0 −38 Original line number Diff line number Diff line Loading @@ -19,10 +19,6 @@ }; }; &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { aqc_x4: aquantia,aqc107@pcie_rc1 { reg = <0 0 0 0 0>; Loading Loading @@ -57,40 +53,6 @@ }; }; &pcie_rc1 { nvme_x8: qcom,nvme@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "qcom,nvme"; pci-ids = "8086:0953", "8086:0a54", "8086:0a55", "8086:f1a5", "8086:f1a5", "1c58:0003", "1c58:0023", "1c5c:1327", "1c5f:0540", "144d:a821", "144d:a822", "144d:a808", "1d1d:1f1f", "1d1d:2807", "1d1d:2601", "106b:2001", "106b:2003", "1179:0115", "1179:0116"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; }; &qupv3_se10_i2c { asm330@6a { qcom,use_qtimer = <1>; /* 0:Disable 1:Enable */ Loading arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi +38 −0 Original line number Diff line number Diff line Loading @@ -292,3 +292,41 @@ qcom,smmu-attr-s1-bypass; }; }; &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { nvme_x8: qcom,nvme@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "qcom,nvme"; pci-ids = "8086:0953", "8086:0a54", "8086:0a55", "8086:f1a5", "8086:f1a5", "1c58:0003", "1c58:0023", "1c5c:1327", "1c5f:0540", "144d:a821", "144d:a822", "144d:a808", "1d1d:1f1f", "1d1d:2807", "1d1d:2601", "106b:2001", "106b:2003", "1179:0115", "1179:0116"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; }; arch/arm64/boot/dts/qcom/sa8155-adp-star.dtsi +0 −38 Original line number Diff line number Diff line Loading @@ -12,41 +12,3 @@ #include "sa8155-adp-common.dtsi" #include "sa8155-adp-star-display.dtsi" &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { nvme_x8: qcom,nvme@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "qcom,nvme"; pci-ids = "8086:0953", "8086:0a54", "8086:0a55", "8086:f1a5", "8086:f1a5", "1c58:0003", "1c58:0023", "1c5c:1327", "1c5f:0540", "144d:a821", "144d:a822", "144d:a808", "1d1d:1f1f", "1d1d:2807", "1d1d:2601", "106b:2001", "106b:2003", "1179:0115", "1179:0116"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; }; Loading
arch/arm64/boot/dts/qcom/sa8155-adp-alcor.dtsi +0 −38 Original line number Diff line number Diff line Loading @@ -19,10 +19,6 @@ }; }; &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { aqc_x4: aquantia,aqc107@pcie_rc1 { reg = <0 0 0 0 0>; Loading Loading @@ -57,40 +53,6 @@ }; }; &pcie_rc1 { nvme_x8: qcom,nvme@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "qcom,nvme"; pci-ids = "8086:0953", "8086:0a54", "8086:0a55", "8086:f1a5", "8086:f1a5", "1c58:0003", "1c58:0023", "1c5c:1327", "1c5f:0540", "144d:a821", "144d:a822", "144d:a808", "1d1d:1f1f", "1d1d:2807", "1d1d:2601", "106b:2001", "106b:2003", "1179:0115", "1179:0116"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; }; &qupv3_se10_i2c { asm330@6a { qcom,use_qtimer = <1>; /* 0:Disable 1:Enable */ Loading
arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi +38 −0 Original line number Diff line number Diff line Loading @@ -292,3 +292,41 @@ qcom,smmu-attr-s1-bypass; }; }; &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { nvme_x8: qcom,nvme@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "qcom,nvme"; pci-ids = "8086:0953", "8086:0a54", "8086:0a55", "8086:f1a5", "8086:f1a5", "1c58:0003", "1c58:0023", "1c5c:1327", "1c5f:0540", "144d:a821", "144d:a822", "144d:a808", "1d1d:1f1f", "1d1d:2807", "1d1d:2601", "106b:2001", "106b:2003", "1179:0115", "1179:0116"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; };
arch/arm64/boot/dts/qcom/sa8155-adp-star.dtsi +0 −38 Original line number Diff line number Diff line Loading @@ -12,41 +12,3 @@ #include "sa8155-adp-common.dtsi" #include "sa8155-adp-star-display.dtsi" &pcie1 { qcom,boot-option = <0x0>; }; &pcie_rc1 { nvme_x8: qcom,nvme@pcie_rc1 { reg = <0 0 0 0 0>; compatible = "qcom,nvme"; pci-ids = "8086:0953", "8086:0a54", "8086:0a55", "8086:f1a5", "8086:f1a5", "1c58:0003", "1c58:0023", "1c5c:1327", "1c5f:0540", "144d:a821", "144d:a822", "144d:a808", "1d1d:1f1f", "1d1d:2807", "1d1d:2601", "106b:2001", "106b:2003", "1179:0115", "1179:0116"; qcom,smmu; qcom,smmu-iova-base = /bits/ 64 <0x20000000>; qcom,smmu-iova-size = /bits/ 64 <0x40000000>; qcom,smmu-attr-atomic; qcom,smmu-attr-s1-bypass; }; };