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Commit cb7418d2 authored by David Collins's avatar David Collins
Browse files

ARM: dts: msm: use VDD_CX, VDD_MX, VDD_MMCX regulator phandles on SDM855 



Switch the regulator supply phandles used for VDD_CX, VDD_MX, and
VDD_MMCX so that device tree configurations are clearer.

Change-Id: Ifd5c4b34c3ed53c929086e3a08a2fec5c3ab77df
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent 8999a2b6

arch/arm64/boot/dts/qcom/sdm855-npu.dtsi

+2 −2
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -26,7 +26,7 @@ 
		clock-names = "xo", "core", "cal_dp", "armwic",

						"axi", "ahb";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

	};

arch/arm64/boot/dts/qcom/sdm855-pcie.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -188,7 +188,7 @@ 
		gdsc-vdd-supply = <&pcie_0_gdsc>;

		vreg-1.8-supply = <&pm855l_l3>;

		vreg-0.9-supply = <&pm855_l5>;

		vreg-cx-supply = <&pm855l_s6_level>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;



		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;

		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;
@@ -478,7 +478,7 @@ 
		gdsc-vdd-supply = <&pcie_1_gdsc>;

		vreg-1.8-supply = <&pm855l_l3>;

		vreg-0.9-supply = <&pm855_l5>;

		vreg-cx-supply = <&pm855l_s6_level>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;



		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;

		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;

arch/arm64/boot/dts/qcom/sdm855-regulator.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -531,7 +531,7 @@ 


		mx_cdev: mx-cdev-lvl {

			compatible = "qcom,regulator-cooling-device";

			regulator-cdev-supply = <&pm855l_s4_level>;

			regulator-cdev-supply = <&VDD_MX_LEVEL>;

			regulator-levels = <RPMH_REGULATOR_LEVEL_NOM

					RPMH_REGULATOR_LEVEL_OFF>;

			#cooling-cells = <2>;
@@ -581,7 +581,7 @@ 


		mm_cx_cdev: mm-cx-cdev-lvl {

			compatible = "qcom,regulator-cooling-device";

			regulator-cdev-supply = <&pm855l_s5_level_ao>;

			regulator-cdev-supply = <&VDD_MMCX_LEVEL_AO>;

			regulator-levels = <RPMH_REGULATOR_LEVEL_NOM

					RPMH_REGULATOR_LEVEL_OFF>;

			#cooling-cells = <2>;
@@ -593,8 +593,8 @@ 
		compatible = "qcom,rpmh-arc-regulator";

		mboxes = <&apps_rsc 0>;

		qcom,resource-name = "cx.lvl";

		pm855l_s6_level-parent-supply = <&pm855l_s4_level>;

		pm855l_s6_level_ao-parent-supply = <&pm855l_s4_level_ao>;

		pm855l_s6_level-parent-supply = <&VDD_MX_LEVEL>;

		pm855l_s6_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>;



		VDD_CX_LEVEL:

		S6C_LEVEL: pm855l_s6_level: regulator-pm855l-s6-level {

arch/arm64/boot/dts/qcom/sdm855-rumi.dtsi

+1 −2
Original line number Diff line number Diff line
@@ -87,8 +87,7 @@ 


#include "sdm855-pmic-overlay.dtsi"



/* VDD_MMCX */

&pm855l_s5_level {

&VDD_MMCX_LEVEL {

	regulator-always-on;

};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+25 −25
Original line number Diff line number Diff line
@@ -1306,9 +1306,9 @@ 
		compatible = "qcom,gcc-sdm855", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx_ao-supply = <&pm855l_s6_level_ao>;

		vdd_mm-supply = <&pm855l_s5_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1317,7 +1317,7 @@ 
		compatible = "qcom,videocc-sdm855", "syscon";

		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

		#clock-cells = <1>;
@@ -1328,8 +1328,8 @@ 
		compatible = "qcom,camcc-sdm855", "syscon";

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&pm855l_s4_level>;

		vdd_mm-supply = <&pm855l_s5_level>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
@@ -1360,7 +1360,7 @@ 
		compatible = "qcom,dispcc-sdm855", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;

		#clock-cells = <1>;
@@ -1371,7 +1371,7 @@ 
		compatible = "qcom,npucc-sdm855", "syscon";

		reg = <0x9910000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_gdsc-supply = <&npu_core_gdsc>;

		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -1381,8 +1381,8 @@ 
		compatible = "qcom,gpucc-sdm855", "syscon";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_mx-supply = <&pm855l_s4_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;

		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -1451,7 +1451,7 @@ 
		clock-names = "xo";

		qcom,proxy-clock-names = "xo";



		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		vdd_mss-supply = <&pm855_s1_level>;

		qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
@@ -1494,7 +1494,7 @@ 
		compatible = "qcom,pil-tz-generic";

		reg = <0x17300000 0x00100>;



		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;

		qcom,proxy-reg-names = "vdd_cx";
@@ -1590,10 +1590,10 @@ 
			    "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";

		interrupts = <0 352 1>;



		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names = "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		vdd_mx-supply = <&pm855l_s4_level>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;



		clocks = <&clock_rpmh RPMH_CXO_CLK>;
@@ -1639,7 +1639,7 @@ 
		compatible = "qcom,pil-tz-generic";

		reg = <0x8300000 0x100000>;



		vdd_cx-supply = <&pm855l_s6_level>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names = "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
@@ -3225,7 +3225,7 @@ 
&bps_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3233,7 +3233,7 @@ 
&ipe_0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3241,7 +3241,7 @@ 
&ipe_1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3249,7 +3249,7 @@ 
&ife_0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3257,7 +3257,7 @@ 
&ife_1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3265,7 +3265,7 @@ 
&titan_top_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3273,7 +3273,7 @@ 
&mdss_core_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_DISP_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3291,7 +3291,7 @@ 
&mvsc_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3299,7 +3299,7 @@ 
&mvs0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};
@@ -3307,7 +3307,7 @@ 
&mvs1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

	parent-supply = <&pm855l_s5_level>;

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,vote-parent-supply-voltage;

	status = "ok";

};