Loading arch/arm64/kernel/cpu_errata.c +6 −0 Original line number Original line Diff line number Diff line Loading @@ -524,6 +524,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(3, 0)), MIDR_CPU_VAR_REV(3, 0)), }, }, { .capability = ARM64_WORKAROUND_REPEAT_TLBI, MIDR_RANGE(MIDR_KRYO4G, MIDR_CPU_VAR_REV(12, 14), MIDR_CPU_VAR_REV(13, 14)), }, #endif #endif #ifdef CONFIG_ARM64_ERRATUM_858921 #ifdef CONFIG_ARM64_ERRATUM_858921 { { Loading Loading
arch/arm64/kernel/cpu_errata.c +6 −0 Original line number Original line Diff line number Diff line Loading @@ -524,6 +524,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(3, 0)), MIDR_CPU_VAR_REV(3, 0)), }, }, { .capability = ARM64_WORKAROUND_REPEAT_TLBI, MIDR_RANGE(MIDR_KRYO4G, MIDR_CPU_VAR_REV(12, 14), MIDR_CPU_VAR_REV(13, 14)), }, #endif #endif #ifdef CONFIG_ARM64_ERRATUM_858921 #ifdef CONFIG_ARM64_ERRATUM_858921 { { Loading