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Commit c3dee4c2 authored by Anant Goel's avatar Anant Goel Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Update entries for serial engine instances 



Update the base address for serial engine instance 15 to
the address specified by the hardware spec. Update the wrapper
node for serial engine instance 13 to use the correct
serial engine wrapper node.

Change-Id: I88264487bbfc361d8ed4b4c689347d5ecab3f538
Signed-off-by: default avatarAnant Goel <anantg@codeaurora.org>
parent 9fcd72d5

arch/arm64/boot/dts/qcom/sa8155-vm-qupv3.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -599,7 +599,7 @@ 
		pinctrl-1 = <&qupv3_se13_spi_sleep>;

		interrupts = <GIC_SPI 585 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};
@@ -740,11 +740,11 @@ 
		status = "disabled";

	};



	qupv3_se15_spi: spi@c90000 {

	qupv3_se15_spi: spi@c94000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xc90000 0x4000>;

		reg = <0xc94000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP2_S5_CLK>,

arch/arm64/boot/dts/qcom/sdmshrike-qupv3.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -605,7 +605,7 @@ 
		pinctrl-1 = <&qupv3_se13_spi_sleep>;

		interrupts = <GIC_SPI 585 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};
@@ -769,11 +769,11 @@ 
		status = "disabled";

	};



	qupv3_se15_spi: spi@c90000 {

	qupv3_se15_spi: spi@c94000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xc90000 0x4000>;

		reg = <0xc94000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,

arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -681,7 +681,7 @@ 
		pinctrl-1 = <&qupv3_se13_spi_sleep>;

		interrupts = <GIC_SPI 585 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		qcom,wrapper-core = <&qupv3_2>;

		dmas = <&gpi_dma2 0 3 1 64 0>,

			<&gpi_dma2 1 3 1 64 0>;

		dma-names = "tx", "rx";
@@ -846,11 +846,11 @@ 
		status = "disabled";

	};



	qupv3_se15_spi: spi@c90000 {

	qupv3_se15_spi: spi@c94000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xc90000 0x4000>;

		reg = <0xc94000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,