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Commit c34151a7 authored by Joerg Roedel's avatar Joerg Roedel Committed by H. Peter Anvin
Browse files

x86, gart: Set DISTLBWALKPRB bit always 



The DISTLBWALKPRB bit must be set for the GART because the
gatt table is mapped UC. But the current code does not set
the bit at boot when the BIOS setup the aperture correctly.
Fix that by setting this bit when enabling the GART instead
of the other places.

Cc: <stable@kernel.org>
Cc: Borislav Petkov <borislav.petkov@amd.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
Link: http://lkml.kernel.org/r/1303134346-5805-4-git-send-email-joerg.roedel@amd.com


Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent af289bfe

arch/x86/include/asm/gart.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -66,7 +66,7 @@ static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order) 
	 * Don't enable translation but enable GART IO and CPU accesses.

	 * Don't enable translation but enable GART IO and CPU accesses.

	 * Also, set DISTLBWALKPRB since GART tables memory is UC.

	 * Also, set DISTLBWALKPRB since GART tables memory is UC.

	 */

	 */

	ctl = DISTLBWALKPRB | order << 1;

	ctl = order << 1;





	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);

	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);

}

}
@@ -83,7 +83,7 @@ static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) 




	/* Enable GART translation for this hammer. */

	/* Enable GART translation for this hammer. */

	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);

	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);

	ctl |= GARTEN;

	ctl |= GARTEN | DISTLBWALKPRB;

	ctl &= ~(DISGARTCPU | DISGARTIO);

	ctl &= ~(DISGARTCPU | DISGARTIO);

	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);

	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);

}

}

arch/x86/kernel/aperture_64.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -499,7 +499,7 @@ int __init gart_iommu_hole_init(void) 
		 * Don't enable translation yet but enable GART IO and CPU

		 * Don't enable translation yet but enable GART IO and CPU

		 * accesses and set DISTLBWALKPRB since GART table memory is UC.

		 * accesses and set DISTLBWALKPRB since GART table memory is UC.

		 */

		 */

		u32 ctl = DISTLBWALKPRB | aper_order << 1;

		u32 ctl = aper_order << 1;





		bus = amd_nb_bus_dev_ranges[i].bus;

		bus = amd_nb_bus_dev_ranges[i].bus;

		dev_base = amd_nb_bus_dev_ranges[i].dev_base;

		dev_base = amd_nb_bus_dev_ranges[i].dev_base;