ARM: dts: msm: Update HS core clk rate for QCS405 USB3

Currently the USB3 primary controller has core clk rate for HS as
10 MHz. This leads to throughput degradation. Update this rate to
100 MHz for better throughput.

Change-Id: I5db9e6f5987b49702c6e8c935ef1735569b459e6
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>