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Commit c11598b5 authored by Vijayanand Jitta's avatar Vijayanand Jitta
Browse files

ARM: dts: msm: Add smmu device for sdm640 



Describe the register address and settings for the
graphics and apps smmu device for sdm640.

Change-Id: I25d9c35d5ca7d2cb35439f5b11650101ffcb6e51
Signed-off-by: default avatarVijayanand Jitta <vjitta@codeaurora.org>
parent 1ef83a2e

arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm640.dtsi

0 → 100644
+214 −0
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



&soc {

	kgsl_smmu: kgsl-smmu@0x50a0000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x50a0000 0x10000>,

			<0x50c2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <1>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		qcom,regulator-names = "vdd";

		vdd-supply = <&gpu_cx_gdsc>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;



		gfx_0_tbu: gfx_0_tbu@0x50c5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x50c5000 0x1000>,

				<0x50c2200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

		};



		gfx_1_tbu: gfx_1_tbu@0x50c9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x50c9000 0x1000>,

				<0x50c2208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

		};

	};



	apps_smmu: apps-smmu@0x15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x80000>,

			<0x150c2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;



		anoc_1_tbu: anoc_1_tbu@0x150c5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150c5000 0x1000>,

				<0x150c2200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;

		};



		anoc_2_tbu: anoc_2_tbu@0x150c9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150c9000 0x1000>,

				<0x150c2208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;

		};



		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150cd000 0x1000>,

				<0x150c2210 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x800 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;

		};



		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150d1000 0x1000>,

				<0x150c2218 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0xc00 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;

		};



		compute_dsp_tbu: compute_dsp_tbu@0x150d5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150d5000 0x1000>,

				<0x150c2220 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1000 0x400>;

			/* No GDSC */

		};



		adsp_tbu: adsp_tbu@0x150d9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150d9000 0x1000>,

				<0x150c2228 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1400 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;

		};

	};



	kgsl_iommu_test_device {

		compatible = "iommu-debug-test";

		/*

		 * 0x7 isn't a valid sid, but should pass the sid sanity check.

		 * We just need _something_ here to get this node recognized by

		 * the SMMU driver. Our test uses ATOS, which doesn't use SIDs

		 * anyways, so using a dummy value is ok.

		 */

		iommus = <&kgsl_smmu 0x7>;

	};



	apps_iommu_test_device {

		compatible = "iommu-debug-test";

		/*

		 * This SID belongs to TSIF. We can't use a fake SID for

		 * the apps_smmu device.

		 */

		iommus = <&apps_smmu 0x20 0>;

	};

};

arch/arm64/boot/dts/qcom/sdm640.dtsi

+1 −0
Original line number Original line Diff line number Diff line
@@ -986,3 +986,4 @@ 
};

};





#include "sdm640-ion.dtsi"

#include "sdm640-ion.dtsi"

#include "msm-arm-smmu-sdm640.dtsi"