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Commit c054065b authored by Kumar Gala's avatar Kumar Gala
Browse files

[POWERPC] 85xx: Add next-level-cache property 



Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec.  Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent acd4b715

arch/powerpc/boot/dts/ksi8560.dts

+2 −1
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
			timebase-frequency = <0>;		/* From U-boot */

			bus-frequency = <0>;			/* From U-boot */

			clock-frequency = <0>;			/* From U-boot */

			next-level-cache = <&L2>;

		};

	};
@@ -62,7 +63,7 @@ 
			interrupts = <0x12 0x2>;

		};



		l2-cache-controller@20000 {

		L2: l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <0x20>;		/* 32 bytes */

arch/powerpc/boot/dts/mpc8540ads.dts

+2 −1
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
			timebase-frequency = <0>;	//  33 MHz, from uboot

			bus-frequency = <0>;	// 166 MHz

			clock-frequency = <0>;	// 825 MHz, from uboot

			next-level-cache = <&L2>;

		};

	};
@@ -63,7 +64,7 @@ 
			interrupts = <18 2>;

		};



		l2-cache-controller@20000 {

		L2: l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

arch/powerpc/boot/dts/mpc8541cds.dts

+2 −1
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
			timebase-frequency = <0>;	//  33 MHz, from uboot

			bus-frequency = <0>;	// 166 MHz

			clock-frequency = <0>;	// 825 MHz, from uboot

			next-level-cache = <&L2>;

		};

	};
@@ -63,7 +64,7 @@ 
			interrupts = <18 2>;

		};



		l2-cache-controller@20000 {

		L2: l2-cache-controller@20000 {

			compatible = "fsl,8541-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

arch/powerpc/boot/dts/mpc8544ds.dts

+2 −1
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
			timebase-frequency = <0>;

			bus-frequency = <0>;

			clock-frequency = <0>;

			next-level-cache = <&L2>;

		};

	};
@@ -65,7 +66,7 @@ 
			interrupts = <18 2>;

		};



		l2-cache-controller@20000 {

		L2: l2-cache-controller@20000 {

			compatible = "fsl,8544-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

arch/powerpc/boot/dts/mpc8548cds.dts

+2 −1
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
			timebase-frequency = <0>;	//  33 MHz, from uboot

			bus-frequency = <0>;	// 166 MHz

			clock-frequency = <0>;	// 825 MHz, from uboot

			next-level-cache = <&L2>;

		};

	};
@@ -68,7 +69,7 @@ 
			interrupts = <18 2>;

		};



		l2-cache-controller@20000 {

		L2: l2-cache-controller@20000 {

			compatible = "fsl,8548-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes