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Commit bef9c558 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6

parents 3db602bd 4b463f78

arch/sparc64/kernel/setup.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -383,6 +383,17 @@ static void __init process_switch(char c) 
		/* Use PROM debug console. */

		/* Use PROM debug console. */

		register_console(&prom_debug_console);

		register_console(&prom_debug_console);

		break;

		break;

	case 'P':

		/* Force UltraSPARC-III P-Cache on. */

		if (tlb_type != cheetah) {

			printk("BOOT: Ignoring P-Cache force option.\n");

			break;

		}

		cheetah_pcache_forced_on = 1;

		add_taint(TAINT_MACHINE_CHECK);

		cheetah_enable_pcache();

		break;



	default:

	default:

		printk("Unknown boot switch (-%c)\n", c);

		printk("Unknown boot switch (-%c)\n", c);

		break;

		break;

arch/sparc64/kernel/smp.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -123,6 +123,9 @@ void __init smp_callin(void) 




	smp_setup_percpu_timer();

	smp_setup_percpu_timer();





	if (cheetah_pcache_forced_on)

		cheetah_enable_pcache();



	local_irq_enable();

	local_irq_enable();





	calibrate_delay();

	calibrate_delay();

arch/sparc64/kernel/traps.c

+19 −0
Original line number Original line Diff line number Diff line
@@ -421,6 +421,25 @@ asmlinkage void cee_log(unsigned long ce_status, 
	}

	}

}

}





int cheetah_pcache_forced_on;



void cheetah_enable_pcache(void)

{

	unsigned long dcr;



	printk("CHEETAH: Enabling P-Cache on cpu %d.\n",

	       smp_processor_id());



	__asm__ __volatile__("ldxa [%%g0] %1, %0"

			     : "=r" (dcr)

			     : "i" (ASI_DCU_CONTROL_REG));

	dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);

	__asm__ __volatile__("stxa %0, [%%g0] %1\n\t"

			     "membar #Sync"

			     : /* no outputs */

			     : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));

}



/* Cheetah error trap handling. */

/* Cheetah error trap handling. */

static unsigned long ecache_flush_physbase;

static unsigned long ecache_flush_physbase;

static unsigned long ecache_flush_linesize;

static unsigned long ecache_flush_linesize;

include/asm-sparc64/spitfire.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -48,6 +48,9 @@ enum ultra_tlb_layout { 




extern enum ultra_tlb_layout tlb_type;

extern enum ultra_tlb_layout tlb_type;





extern int cheetah_pcache_forced_on;

extern void cheetah_enable_pcache(void);



#define sparc64_highest_locked_tlbent()	\

#define sparc64_highest_locked_tlbent()	\

	(tlb_type == spitfire ? \

	(tlb_type == spitfire ? \

	 SPITFIRE_HIGHEST_LOCKED_TLBENT : \

	 SPITFIRE_HIGHEST_LOCKED_TLBENT : \