Commit be8408e1 authored Jun 06, 2017 by Jiri Pirko Committed by David S. Miller Jun 06, 2017

mlxsw: pci: Fix size of trap_id field in CQE



The "trap_id" is 9bits long. So far, this was not a problem since we
used only traps with ids that fit into 8bits. But the ACL traps that are
going to be introduced use the 9th bit.

Fixes: eda6500a ("mlxsw: Add PCI bus implementation")
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Yotam Gigi <yotamg@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 5a4d1fee

drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -155,7 +155,7 @@ MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
		/* pci_cqe_trap_id
		* Trap ID that captured the packet.
		*/
		MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
		MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);

		/* pci_cqe_crc
		* Length include CRC. Indicates the length field includes