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Commit bc436b17 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable virtio clock for sa8195 vm"

parents 2b272a0c 9b913d10

arch/arm64/boot/dts/qcom/sa8195-vm.dtsi

+8 −5
Original line number Diff line number Diff line
@@ -31,16 +31,19 @@ 
};



&soc {

	clock_virt: qcom,virt-gcc {

		compatible = "qcom,virt-clk-sm8150-gcc";

	clock_virt: qcom,virtio-gcc {

		compatible = "virtio,mmio";

		reg = <0x1c200000 0x1000>;

		interrupts = <0 48 0>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_virt_scc: qcom,virt-scc {

		compatible = "qcom,virt-clk-sm8150-scc";

	clock_virt_scc: qcom,virtio-scc {

		compatible = "virtio,mmio";

		reg = <0x1c300000 0x1000>;

		interrupts = <0 49 0>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	apps_smmu: apps-smmu@0x15000000 {

drivers/clk/qcom/virtio_clk_sa8195p.c

+17 −0
Original line number Diff line number Diff line
@@ -45,11 +45,26 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { 
	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = "gcc_cfg_noc_usb3_prim_axi_clk",

	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = "gcc_aggre_usb3_prim_axi_clk",

	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = "gcc_usb30_prim_mock_utmi_clk",

	[GCC_USB30_PRIM_SLEEP_CLK] = "gcc_usb30_prim_sleep_clk",

	[GCC_USB3_PRIM_PHY_AUX_CLK] = "gcc_usb3_prim_phy_aux_clk",

	[GCC_USB3_PRIM_PHY_PIPE_CLK] = "gcc_usb3_prim_phy_pipe_clk",

	[GCC_USB3_PRIM_CLKREF_CLK] = "gcc_usb3_prim_clkref_en",

	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = "gcc_usb3_prim_phy_com_aux_clk",

	[GCC_USB30_SEC_MASTER_CLK] = "gcc_usb30_sec_master_clk",

	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = "gcc_cfg_noc_usb3_sec_axi_clk",

	[GCC_AGGRE_USB3_SEC_AXI_CLK] = "gcc_aggre_usb3_sec_axi_clk",

	[GCC_USB30_SEC_MOCK_UTMI_CLK] = "gcc_usb30_sec_mock_utmi_clk",

	[GCC_USB30_SEC_SLEEP_CLK] = "gcc_usb30_sec_sleep_clk",

	[GCC_USB3_SEC_PHY_AUX_CLK] = "gcc_usb3_sec_phy_aux_clk",

	[GCC_USB3_SEC_PHY_PIPE_CLK] = "gcc_usb3_sec_phy_pipe_clk",

	[GCC_USB3_SEC_CLKREF_CLK] = "gcc_usb3_sec_clkref_en",

	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = "gcc_usb3_sec_phy_com_aux_clk",

	[GCC_PCIE_0_PIPE_CLK] = "gcc_pcie_0_pipe_clk",

	[GCC_PCIE_0_AUX_CLK] = "gcc_pcie_0_aux_clk",

	[GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk",

	[GCC_PCIE_0_MSTR_AXI_CLK] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk",

	[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en",

	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk",

	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = "gcc_aggre_noc_pcie_tbu_clk",

	[GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk",
@@ -60,7 +75,9 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { 


static const char * const sa8195p_gcc_virtio_resets[] = {

	[GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr",

	[GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr",

	[GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk",

	[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",

	[GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",

};