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Commit ba289af8 authored by Roger Chen's avatar Roger Chen Committed by David S. Miller
Browse files

net: stmmac: dwmac-rk: add rk3366 & rk3399 specific data 



Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.

Signed-off-by: default avatarRoger Chen <roger.chen@rock-chips.com>
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent dd19bde3

Documentation/devicetree/bindings/net/rockchip-dwmac.txt

+6 −2
Original line number Diff line number Diff line
@@ -3,8 +3,12 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC) 
The device node has following properties.



Required properties:

 - compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",

                             "rockchip,rk3368-gmac"

 - compatible: should be "rockchip,<name>-gamc"

   "rockchip,rk3228-gmac": found on RK322x SoCs

   "rockchip,rk3288-gmac": found on RK3288 SoCs

   "rockchip,rk3366-gmac": found on RK3366 SoCs

   "rockchip,rk3368-gmac": found on RK3368 SoCs

   "rockchip,rk3399-gmac": found on RK3399 SoCs

 - reg: addresses and length of the register sets for the device.

 - interrupts: Should contain the GMAC interrupts.

 - interrupt-names: Should contain the interrupt names "macirq".

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

+226 −0
Original line number Diff line number Diff line
@@ -301,6 +301,118 @@ static const struct rk_gmac_ops rk3288_ops = { 
	.set_rmii_speed = rk3288_set_rmii_speed,

};



#define RK3366_GRF_SOC_CON6	0x0418

#define RK3366_GRF_SOC_CON7	0x041c



/* RK3366_GRF_SOC_CON6 */

#define RK3366_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \

					 GRF_CLR_BIT(11))

#define RK3366_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \

					 GRF_BIT(11))

#define RK3366_GMAC_FLOW_CTRL		GRF_BIT(8)

#define RK3366_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)

#define RK3366_GMAC_SPEED_10M		GRF_CLR_BIT(7)

#define RK3366_GMAC_SPEED_100M		GRF_BIT(7)

#define RK3366_GMAC_RMII_CLK_25M	GRF_BIT(3)

#define RK3366_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)

#define RK3366_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))

#define RK3366_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))

#define RK3366_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))

#define RK3366_GMAC_RMII_MODE		GRF_BIT(6)

#define RK3366_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)



/* RK3366_GRF_SOC_CON7 */

#define RK3366_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)

#define RK3366_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)

#define RK3366_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)

#define RK3366_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)

#define RK3366_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)

#define RK3366_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)



static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,

				int tx_delay, int rx_delay)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,

		     RK3366_GMAC_PHY_INTF_SEL_RGMII |

		     RK3366_GMAC_RMII_MODE_CLR);

	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,

		     RK3366_GMAC_RXCLK_DLY_ENABLE |

		     RK3366_GMAC_TXCLK_DLY_ENABLE |

		     RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |

		     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,

		     RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);

}



static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	if (speed == 10)

		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,

			     RK3366_GMAC_CLK_2_5M);

	else if (speed == 100)

		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,

			     RK3366_GMAC_CLK_25M);

	else if (speed == 1000)

		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,

			     RK3366_GMAC_CLK_125M);

	else

		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);

}



static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	if (speed == 10) {

		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,

			     RK3366_GMAC_RMII_CLK_2_5M |

			     RK3366_GMAC_SPEED_10M);

	} else if (speed == 100) {

		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,

			     RK3366_GMAC_RMII_CLK_25M |

			     RK3366_GMAC_SPEED_100M);

	} else {

		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);

	}

}



static const struct rk_gmac_ops rk3366_ops = {

	.set_to_rgmii = rk3366_set_to_rgmii,

	.set_to_rmii = rk3366_set_to_rmii,

	.set_rgmii_speed = rk3366_set_rgmii_speed,

	.set_rmii_speed = rk3366_set_rmii_speed,

};



#define RK3368_GRF_SOC_CON15	0x043c

#define RK3368_GRF_SOC_CON16	0x0440
@@ -413,6 +525,118 @@ static const struct rk_gmac_ops rk3368_ops = { 
	.set_rmii_speed = rk3368_set_rmii_speed,

};



#define RK3399_GRF_SOC_CON5	0xc214

#define RK3399_GRF_SOC_CON6	0xc218



/* RK3399_GRF_SOC_CON5 */

#define RK3399_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \

					 GRF_CLR_BIT(11))

#define RK3399_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \

					 GRF_BIT(11))

#define RK3399_GMAC_FLOW_CTRL		GRF_BIT(8)

#define RK3399_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)

#define RK3399_GMAC_SPEED_10M		GRF_CLR_BIT(7)

#define RK3399_GMAC_SPEED_100M		GRF_BIT(7)

#define RK3399_GMAC_RMII_CLK_25M	GRF_BIT(3)

#define RK3399_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)

#define RK3399_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))

#define RK3399_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))

#define RK3399_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))

#define RK3399_GMAC_RMII_MODE		GRF_BIT(6)

#define RK3399_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)



/* RK3399_GRF_SOC_CON6 */

#define RK3399_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)

#define RK3399_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)

#define RK3399_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)

#define RK3399_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)

#define RK3399_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)

#define RK3399_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)



static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,

				int tx_delay, int rx_delay)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,

		     RK3399_GMAC_PHY_INTF_SEL_RGMII |

		     RK3399_GMAC_RMII_MODE_CLR);

	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,

		     RK3399_GMAC_RXCLK_DLY_ENABLE |

		     RK3399_GMAC_TXCLK_DLY_ENABLE |

		     RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |

		     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,

		     RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);

}



static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	if (speed == 10)

		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,

			     RK3399_GMAC_CLK_2_5M);

	else if (speed == 100)

		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,

			     RK3399_GMAC_CLK_25M);

	else if (speed == 1000)

		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,

			     RK3399_GMAC_CLK_125M);

	else

		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);

}



static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (IS_ERR(bsp_priv->grf)) {

		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);

		return;

	}



	if (speed == 10) {

		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,

			     RK3399_GMAC_RMII_CLK_2_5M |

			     RK3399_GMAC_SPEED_10M);

	} else if (speed == 100) {

		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,

			     RK3399_GMAC_RMII_CLK_25M |

			     RK3399_GMAC_SPEED_100M);

	} else {

		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);

	}

}



static const struct rk_gmac_ops rk3399_ops = {

	.set_to_rgmii = rk3399_set_to_rgmii,

	.set_to_rmii = rk3399_set_to_rmii,

	.set_rgmii_speed = rk3399_set_rgmii_speed,

	.set_rmii_speed = rk3399_set_rmii_speed,

};



static int gmac_clk_init(struct rk_priv_data *bsp_priv)

{

	struct device *dev = &bsp_priv->pdev->dev;
@@ -760,7 +984,9 @@ static int rk_gmac_probe(struct platform_device *pdev) 
static const struct of_device_id rk_gmac_dwmac_match[] = {

	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },

	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },

	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },

	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },

	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },

	{ }

};

MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);