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Commit b98e3803 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "UPSTREAM: ath10k: Add support for 64 bit HTT frag descriptor"

parents e964e609 afd87f15

drivers/net/wireless/ath/ath10k/core.c

+13 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA9887_HW_1_0_VERSION,
@@ -105,6 +106,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA6174_HW_2_1_VERSION,
@@ -131,6 +133,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA6174_HW_2_1_VERSION,
@@ -157,6 +160,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA6174_HW_3_0_VERSION,
@@ -183,6 +187,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA6174_HW_3_2_VERSION,
@@ -212,6 +217,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA99X0_HW_2_0_DEV_VERSION,
@@ -244,6 +250,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA9984_HW_1_0_DEV_VERSION,
@@ -281,6 +288,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA9888_HW_2_0_DEV_VERSION,
@@ -317,6 +325,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA9377_HW_1_0_DEV_VERSION,
@@ -343,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA9377_HW_1_1_DEV_VERSION,
@@ -371,6 +381,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = QCA4019_HW_1_0_DEV_VERSION,
@@ -404,6 +415,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_TLV_NUM_PEERS,

		.ast_skid_limit = 0x10,

		.num_wds_entries = 0x20,

		.target_64bit = false,

	},

	{

		.id = WCN3990_HW_1_0_DEV_VERSION,
@@ -422,6 +434,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_peers = TARGET_HL_10_TLV_NUM_PEERS,

		.ast_skid_limit = TARGET_HL_10_TLV_AST_SKID_LIMIT,

		.num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES,

		.target_64bit = true,

	},

};

drivers/net/wireless/ath/ath10k/htt.c

+4 −2
Original line number Diff line number Diff line
@@ -207,6 +207,8 @@ int ath10k_htt_init(struct ath10k *ar) 
		WARN_ON(1);

		return -EINVAL;

	}

	ath10k_htt_set_tx_ops(htt);



	return 0;

}
@@ -254,11 +256,11 @@ int ath10k_htt_setup(struct ath10k_htt *htt) 
		return status;

	}



	status = ath10k_htt_send_frag_desc_bank_cfg(htt);

	status = htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);

	if (status)

		return status;



	status = ath10k_htt_send_rx_ring_cfg_ll(htt);

	status = htt->tx_ops->htt_send_rx_ring_cfg(htt);

	if (status) {

		ath10k_warn(ar, "failed to setup rx ring: %d\n",

			    status);

drivers/net/wireless/ath/ath10k/htt.h

+76 −10
Original line number Diff line number Diff line
@@ -107,6 +107,14 @@ struct htt_msdu_ext_desc { 
	struct htt_data_tx_desc_frag frags[6];

};



struct htt_msdu_ext_desc_64 {

	__le32 tso_flag[5];

	__le16 ip_identification;

	u8 flags;

	u8 reserved;

	struct htt_data_tx_desc_frag frags[6];

};



#define	HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE		BIT(0)

#define	HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE	BIT(1)

#define	HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE	BIT(2)
@@ -201,7 +209,7 @@ enum htt_rx_ring_flags { 
#define HTT_RX_RING_SIZE_MIN 128

#define HTT_RX_RING_SIZE_MAX 2048



struct htt_rx_ring_setup_ring {

struct htt_rx_ring_setup_ring32 {

	__le32 fw_idx_shadow_reg_paddr;

	__le32 rx_ring_base_paddr;

	__le16 rx_ring_len; /* in 4-byte words */
@@ -222,14 +230,40 @@ struct htt_rx_ring_setup_ring { 
	__le16 frag_info_offset;

} __packed;



struct htt_rx_ring_setup_ring64 {

	__le64 fw_idx_shadow_reg_paddr;

	__le64 rx_ring_base_paddr;

	__le16 rx_ring_len; /* in 4-byte words */

	__le16 rx_ring_bufsize; /* rx skb size - in bytes */

	__le16 flags; /* %HTT_RX_RING_FLAGS_ */

	__le16 fw_idx_init_val;



	/* the following offsets are in 4-byte units */

	__le16 mac80211_hdr_offset;

	__le16 msdu_payload_offset;

	__le16 ppdu_start_offset;

	__le16 ppdu_end_offset;

	__le16 mpdu_start_offset;

	__le16 mpdu_end_offset;

	__le16 msdu_start_offset;

	__le16 msdu_end_offset;

	__le16 rx_attention_offset;

	__le16 frag_info_offset;

} __packed;



struct htt_rx_ring_setup_hdr {

	u8 num_rings; /* supported values: 1, 2 */

	__le16 rsvd0;

} __packed;



struct htt_rx_ring_setup {

struct htt_rx_ring_setup_32 {

	struct htt_rx_ring_setup_hdr hdr;

	struct htt_rx_ring_setup_ring32 rings[0];

} __packed;



struct htt_rx_ring_setup_64 {

	struct htt_rx_ring_setup_hdr hdr;

	struct htt_rx_ring_setup_ring rings[0];

	struct htt_rx_ring_setup_ring64 rings[0];

} __packed;



/*
@@ -855,13 +889,23 @@ struct htt_rx_in_ord_msdu_desc { 
	u8 reserved;

} __packed;



struct htt_rx_in_ord_msdu_desc_ext {

	__le64 msdu_paddr;

	__le16 msdu_len;

	u8 fw_desc;

	u8 reserved;

} __packed;



struct htt_rx_in_ord_ind {

	u8 info;

	__le16 peer_id;

	u8 vdev_id;

	u8 reserved;

	__le16 msdu_count;

	struct htt_rx_in_ord_msdu_desc msdu_descs[0];

	union {

		struct htt_rx_in_ord_msdu_desc msdu_descs32[0];

		struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0];

	} __packed;

} __packed;



#define HTT_RX_IN_ORD_IND_INFO_TID_MASK		0x0000001f
@@ -1351,7 +1395,7 @@ struct htt_q_state_conf { 
	u8 pad[2];

} __packed;



struct htt_frag_desc_bank_cfg {

struct htt_frag_desc_bank_cfg32 {

	u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */

	u8 num_banks;

	u8 desc_size;
@@ -1360,6 +1404,15 @@ struct htt_frag_desc_bank_cfg { 
	struct htt_q_state_conf q_state;

} __packed;



struct htt_frag_desc_bank_cfg64 {

	u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */

	u8 num_banks;

	u8 desc_size;

	__le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];

	struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];

	struct htt_q_state_conf q_state;

} __packed;



#define HTT_TX_Q_STATE_ENTRY_COEFFICIENT	128

#define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK	0x3f

#define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB		0
@@ -1531,11 +1584,13 @@ struct htt_cmd { 
		struct htt_ver_req ver_req;

		struct htt_mgmt_tx_desc mgmt_tx;

		struct htt_data_tx_desc data_tx;

		struct htt_rx_ring_setup rx_setup;

		struct htt_rx_ring_setup_32 rx_setup_32;

		struct htt_rx_ring_setup_64 rx_setup_64;

		struct htt_stats_req stats_req;

		struct htt_oob_sync_req oob_sync_req;

		struct htt_aggr_conf aggr_conf;

		struct htt_frag_desc_bank_cfg frag_desc_bank_cfg;

		struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32;

		struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64;

		struct htt_tx_fetch_resp tx_fetch_resp;

	};

} __packed;
@@ -1721,7 +1776,11 @@ struct ath10k_htt { 


	struct {

		dma_addr_t paddr;

		struct htt_msdu_ext_desc *vaddr;

		union {

			struct htt_msdu_ext_desc *vaddr_desc_32;

			struct htt_msdu_ext_desc_64 *vaddr_desc_64;

		};

		size_t size;

	} frag_desc;



	struct {
@@ -1741,6 +1800,14 @@ struct ath10k_htt { 
	} tx_q_state;



	bool tx_mem_allocated;

	const struct ath10k_htt_tx_ops *tx_ops;

};



struct ath10k_htt_tx_ops {

	int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt);

	int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt);

	int (*htt_alloc_frag_desc)(struct ath10k_htt *htt);

	void (*htt_free_frag_desc)(struct ath10k_htt *htt);

};



#define RX_HTT_HDR_STATUS_LEN 64
@@ -1820,7 +1887,6 @@ void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 
bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);

int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);

int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie);

int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt);

int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt);

int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,

				u8 max_subfrms_ampdu,
@@ -1852,5 +1918,5 @@ int ath10k_htt_tx(struct ath10k_htt *htt, 
void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,

					     struct sk_buff *skb);

int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget);



void ath10k_htt_set_tx_ops(struct ath10k_htt *htt);

#endif

drivers/net/wireless/ath/ath10k/htt_rx.c

+61 −6
Original line number Diff line number Diff line
@@ -411,12 +411,12 @@ static struct sk_buff *ath10k_htt_rx_pop_paddr(struct ath10k_htt *htt, 
	return msdu;

}



static int ath10k_htt_rx_pop_paddr_list(struct ath10k_htt *htt,

static int ath10k_htt_rx_pop_paddr32_list(struct ath10k_htt *htt,

					  struct htt_rx_in_ord_ind *ev,

					  struct sk_buff_head *list)

{

	struct ath10k *ar = htt->ar;

	struct htt_rx_in_ord_msdu_desc *msdu_desc = ev->msdu_descs;

	struct htt_rx_in_ord_msdu_desc *msdu_desc = ev->msdu_descs32;

	struct htt_rx_desc *rxd;

	struct sk_buff *msdu;

	int msdu_count;
@@ -461,6 +461,55 @@ static int ath10k_htt_rx_pop_paddr_list(struct ath10k_htt *htt, 
	return 0;

}



static int ath10k_htt_rx_pop_paddr64_list(struct ath10k_htt *htt,

					  struct htt_rx_in_ord_ind *ev,

					  struct sk_buff_head *list)

{

	struct ath10k *ar = htt->ar;

	struct htt_rx_in_ord_msdu_desc_ext *msdu_desc = ev->msdu_descs64;

	struct htt_rx_desc *rxd;

	struct sk_buff *msdu;

	int msdu_count;

	bool is_offload;

	u64 paddr;



	lockdep_assert_held(&htt->rx_ring.lock);



	msdu_count = __le16_to_cpu(ev->msdu_count);

	is_offload = !!(ev->info & HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK);



	while (msdu_count--) {

		paddr = __le64_to_cpu(msdu_desc->msdu_paddr);

		msdu = ath10k_htt_rx_pop_paddr(htt, paddr);

		if (!msdu) {

			__skb_queue_purge(list);

			return -ENOENT;

		}



		__skb_queue_tail(list, msdu);



		if (!is_offload) {

			rxd = (void *)msdu->data;



			trace_ath10k_htt_rx_desc(ar, rxd, sizeof(*rxd));



			skb_put(msdu, sizeof(*rxd));

			skb_pull(msdu, sizeof(*rxd));

			skb_put(msdu, __le16_to_cpu(msdu_desc->msdu_len));



			if (!(__le32_to_cpu(rxd->attention.flags) &

			      RX_ATTENTION_FLAGS_MSDU_DONE)) {

				ath10k_warn(htt->ar, "tried to pop an incomplete frame, oops!\n");

				return -EIO;

			}

		}



		msdu_desc++;

	}



	return 0;

}



int ath10k_htt_rx_alloc(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;
@@ -1964,7 +2013,7 @@ static int ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) 
		   "htt rx in ord vdev %i peer %i tid %i offload %i frag %i msdu count %i\n",

		   vdev_id, peer_id, tid, offload, frag, msdu_count);



	if (skb->len < msdu_count * sizeof(*resp->rx_in_ord_ind.msdu_descs)) {

	if (skb->len < msdu_count * sizeof(*resp->rx_in_ord_ind.msdu_descs32)) {

		ath10k_warn(ar, "dropping invalid in order rx indication\n");

		return -EINVAL;

	}
@@ -1973,7 +2022,13 @@ static int ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) 
	 * extracted and processed.

	 */

	__skb_queue_head_init(&list);

	ret = ath10k_htt_rx_pop_paddr_list(htt, &resp->rx_in_ord_ind, &list);

	if (ar->hw_params.target_64bit)

		ret = ath10k_htt_rx_pop_paddr64_list(htt, &resp->rx_in_ord_ind,

						     &list);

	else

		ret = ath10k_htt_rx_pop_paddr32_list(htt, &resp->rx_in_ord_ind,

						     &list);



	if (ret < 0) {

		ath10k_warn(ar, "failed to pop paddr list: %d\n", ret);

		htt->rx_confused = true;

drivers/net/wireless/ath/ath10k/htt_tx.c

+266 −38
Original line number Diff line number Diff line
@@ -256,23 +256,25 @@ static int ath10k_htt_tx_alloc_cont_txbuf(struct ath10k_htt *htt) 
	return 0;

}



static void ath10k_htt_tx_free_cont_frag_desc(struct ath10k_htt *htt)

static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt)

{

	size_t size;



	if (!htt->frag_desc.vaddr)

	if (!htt->frag_desc.vaddr_desc_32)

		return;



	size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc);

	size = htt->max_num_pending_tx *

			sizeof(struct htt_msdu_ext_desc);



	dma_free_coherent(htt->ar->dev,

			  size,

			  htt->frag_desc.vaddr,

			  htt->frag_desc.vaddr_desc_32,

			  htt->frag_desc.paddr);

	htt->frag_desc.vaddr = NULL;



	htt->frag_desc.vaddr_desc_32 = NULL;

}



static int ath10k_htt_tx_alloc_cont_frag_desc(struct ath10k_htt *htt)

static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;

	size_t size;
@@ -280,12 +282,57 @@ static int ath10k_htt_tx_alloc_cont_frag_desc(struct ath10k_htt *htt) 
	if (!ar->hw_params.continuous_frag_desc)

		return 0;



	size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc);

	htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size,

	size = htt->max_num_pending_tx *

			sizeof(struct htt_msdu_ext_desc);

	htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size,

							  &htt->frag_desc.paddr,

							  GFP_KERNEL);

	if (!htt->frag_desc.vaddr)

	if (!htt->frag_desc.vaddr_desc_32) {

		ath10k_err(ar, "failed to alloc fragment desc memory\n");

		return -ENOMEM;

	}

	htt->frag_desc.size = size;



	return 0;

}



static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt)

{

	size_t size;



	if (!htt->frag_desc.vaddr_desc_64)

		return;



	size = htt->max_num_pending_tx *

			sizeof(struct htt_msdu_ext_desc_64);



	dma_free_coherent(htt->ar->dev,

			  size,

			  htt->frag_desc.vaddr_desc_64,

			  htt->frag_desc.paddr);



	htt->frag_desc.vaddr_desc_64 = NULL;

}



static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;

	size_t size;



	if (!ar->hw_params.continuous_frag_desc)

		return 0;



	size = htt->max_num_pending_tx *

			sizeof(struct htt_msdu_ext_desc_64);



	htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size,

							  &htt->frag_desc.paddr,

							  GFP_KERNEL);

	if (!htt->frag_desc.vaddr_desc_64) {

		ath10k_err(ar, "failed to alloc fragment desc memory\n");

		return -ENOMEM;

	}

	htt->frag_desc.size = size;



	return 0;

}
@@ -363,7 +410,7 @@ static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 
		return ret;

	}



	ret = ath10k_htt_tx_alloc_cont_frag_desc(htt);

	ret = htt->tx_ops->htt_alloc_frag_desc(htt);

	if (ret) {

		ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret);

		goto free_txbuf;
@@ -387,7 +434,7 @@ static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 
	ath10k_htt_tx_free_txq(htt);



free_frag_desc:

	ath10k_htt_tx_free_cont_frag_desc(htt);

	htt->tx_ops->htt_free_frag_desc(htt);



free_txbuf:

	ath10k_htt_tx_free_cont_txbuf(htt);
@@ -446,7 +493,7 @@ void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 


	ath10k_htt_tx_free_cont_txbuf(htt);

	ath10k_htt_tx_free_txq(htt);

	ath10k_htt_tx_free_cont_frag_desc(htt);

	htt->tx_ops->htt_free_frag_desc(htt);

	ath10k_htt_tx_free_txdone_fifo(htt);

	htt->tx_mem_allocated = false;

}
@@ -545,12 +592,12 @@ int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie) 
	return 0;

}



int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)

static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;

	struct sk_buff *skb;

	struct htt_cmd *cmd;

	struct htt_frag_desc_bank_cfg *cfg;

	struct htt_frag_desc_bank_cfg32 *cfg;

	int ret, size;

	u8 info;
@@ -562,7 +609,7 @@ int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 
		return -EINVAL;

	}



	size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg);

	size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32);

	skb = ath10k_htc_alloc_skb(ar, size);

	if (!skb)

		return -ENOMEM;
@@ -579,7 +626,7 @@ int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 
		     ar->running_fw->fw_file.fw_features))

		info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;



	cfg = &cmd->frag_desc_bank_cfg;

	cfg = &cmd->frag_desc_bank_cfg32;

	cfg->info = info;

	cfg->num_banks = 1;

	cfg->desc_size = sizeof(struct htt_msdu_ext_desc);
@@ -607,12 +654,112 @@ int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 
	return 0;

}



int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)

static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;

	struct sk_buff *skb;

	struct htt_cmd *cmd;

	struct htt_rx_ring_setup_ring *ring;

	struct htt_frag_desc_bank_cfg64 *cfg;

	int ret, size;

	u8 info;



	if (!ar->hw_params.continuous_frag_desc)

		return 0;



	if (!htt->frag_desc.paddr) {

		ath10k_warn(ar, "invalid frag desc memory\n");

		return -EINVAL;

	}



	size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64);

	skb = ath10k_htc_alloc_skb(ar, size);

	if (!skb)

		return -ENOMEM;



	skb_put(skb, size);

	cmd = (struct htt_cmd *)skb->data;

	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;



	info = 0;

	info |= SM(htt->tx_q_state.type,

		   HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE);



	if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,

		     ar->running_fw->fw_file.fw_features))

		info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;



	cfg = &cmd->frag_desc_bank_cfg64;

	cfg->info = info;

	cfg->num_banks = 1;

	cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64);

	cfg->bank_base_addrs[0] =  __cpu_to_le64(htt->frag_desc.paddr);

	cfg->bank_id[0].bank_min_id = 0;

	cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx -

						    1);



	cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr);

	cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers);

	cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids);

	cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE;

	cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER;



	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n");



	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);

	if (ret) {

		ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",

			    ret);

		dev_kfree_skb_any(skb);

		return ret;

	}



	return 0;

}



static void ath10k_htt_fill_rx_desc_offset_32(void *rx_ring)

{

	struct htt_rx_ring_setup_ring32 *ring =

			(struct htt_rx_ring_setup_ring32 *)rx_ring;



#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)

	ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));

	ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));

	ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));

	ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));

	ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));

	ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));

	ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));

	ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));

	ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));

	ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));

#undef desc_offset

}



static void ath10k_htt_fill_rx_desc_offset_64(void *rx_ring)

{

	struct htt_rx_ring_setup_ring64 *ring =

			(struct htt_rx_ring_setup_ring64 *)rx_ring;



#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)

	ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));

	ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));

	ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));

	ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));

	ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));

	ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));

	ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));

	ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));

	ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));

	ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));

#undef desc_offset

}



static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;

	struct sk_buff *skb;

	struct htt_cmd *cmd;

	struct htt_rx_ring_setup_ring32 *ring;

	const int num_rx_ring = 1;

	u16 flags;

	u32 fw_idx;
@@ -626,7 +773,7 @@ int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt) 
	BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));

	BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);



	len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)

	len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr)

	    + (sizeof(*ring) * num_rx_ring);

	skb = ath10k_htc_alloc_skb(ar, len);

	if (!skb)
@@ -635,10 +782,10 @@ int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt) 
	skb_put(skb, len);



	cmd = (struct htt_cmd *)skb->data;

	ring = &cmd->rx_setup.rings[0];

	ring = &cmd->rx_setup_32.rings[0];



	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;

	cmd->rx_setup.hdr.num_rings = 1;

	cmd->rx_setup_32.hdr.num_rings = 1;



	/* FIXME: do we need all of this? */

	flags = 0;
@@ -669,21 +816,76 @@ int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt) 
	ring->flags = __cpu_to_le16(flags);

	ring->fw_idx_init_val = __cpu_to_le16(fw_idx);



#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)

	ath10k_htt_fill_rx_desc_offset_32(ring);

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);

	if (ret) {

		dev_kfree_skb_any(skb);

		return ret;

	}



	ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));

	ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));

	ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));

	ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));

	ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));

	ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));

	ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));

	ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));

	ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));

	ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));

	return 0;

}



#undef desc_offset

static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;

	struct sk_buff *skb;

	struct htt_cmd *cmd;

	struct htt_rx_ring_setup_ring64 *ring;

	const int num_rx_ring = 1;

	u16 flags;

	u32 fw_idx;

	int len;

	int ret;



	/* HW expects the buffer to be an integral number of 4-byte

	 * "words"

	 */

	BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));

	BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);



	len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr)

	    + (sizeof(*ring) * num_rx_ring);

	skb = ath10k_htc_alloc_skb(ar, len);

	if (!skb)

		return -ENOMEM;



	skb_put(skb, len);



	cmd = (struct htt_cmd *)skb->data;

	ring = &cmd->rx_setup_64.rings[0];



	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;

	cmd->rx_setup_64.hdr.num_rings = 1;



	flags = 0;

	flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;

	flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;

	flags |= HTT_RX_RING_FLAGS_PPDU_START;

	flags |= HTT_RX_RING_FLAGS_PPDU_END;

	flags |= HTT_RX_RING_FLAGS_MPDU_START;

	flags |= HTT_RX_RING_FLAGS_MPDU_END;

	flags |= HTT_RX_RING_FLAGS_MSDU_START;

	flags |= HTT_RX_RING_FLAGS_MSDU_END;

	flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;

	flags |= HTT_RX_RING_FLAGS_FRAG_INFO;

	flags |= HTT_RX_RING_FLAGS_UNICAST_RX;

	flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;

	flags |= HTT_RX_RING_FLAGS_CTRL_RX;

	flags |= HTT_RX_RING_FLAGS_MGMT_RX;

	flags |= HTT_RX_RING_FLAGS_NULL_RX;

	flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;



	fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);



	ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr);

	ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr);

	ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);

	ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);

	ring->flags = __cpu_to_le16(flags);

	ring->fw_idx_init_val = __cpu_to_le16(fw_idx);



	ath10k_htt_fill_rx_desc_offset_64(ring);

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);

	if (ret) {

		dev_kfree_skb_any(skb);
@@ -917,6 +1119,7 @@ int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 
	u32 frags_paddr = 0;

	u32 txbuf_paddr;

	struct htt_msdu_ext_desc *ext_desc = NULL;

	struct htt_msdu_ext_desc *ext_desc_t = NULL;



	spin_lock_bh(&htt->tx_lock);

	res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
@@ -962,11 +1165,12 @@ int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 
		/* pass through */

	case ATH10K_HW_TXRX_ETHERNET:

		if (ar->hw_params.continuous_frag_desc) {

			memset(&htt->frag_desc.vaddr[msdu_id], 0,

			ext_desc_t = htt->frag_desc.vaddr_desc_32;

			memset(&ext_desc_t[msdu_id], 0,

			       sizeof(struct htt_msdu_ext_desc));

			frags = (struct htt_data_tx_desc_frag *)

				&htt->frag_desc.vaddr[msdu_id].frags;

			ext_desc = &htt->frag_desc.vaddr[msdu_id];

				&ext_desc_t[msdu_id].frags;

			ext_desc = &ext_desc_t[msdu_id];

			frags[0].tword_addr.paddr_lo =

				__cpu_to_le32(skb_cb->paddr);

			frags[0].tword_addr.paddr_hi = 0;
@@ -1093,3 +1297,27 @@ int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 
err:

	return res;

}



static const struct ath10k_htt_tx_ops htt_tx_ops_32 = {

	.htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32,

	.htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32,

	.htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32,

	.htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32,

};



static const struct ath10k_htt_tx_ops htt_tx_ops_64 = {

	.htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64,

	.htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64,

	.htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64,

	.htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64,

};



void ath10k_htt_set_tx_ops(struct ath10k_htt *htt)

{

	struct ath10k *ar = htt->ar;



	if (ar->hw_params.target_64bit)

		htt->tx_ops = &htt_tx_ops_64;

	else

		htt->tx_ops = &htt_tx_ops_32;

}