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Commit b976dc53 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake. 



Along with GLK it was introduced the .is_lp and IS_GEN9_LP.
So, following the same simplification standard we can
put Skylake and Kabylake under the same bucket for most
of the things.

So let's add the IS_GEN9_BC for "Big Core" (non Atom based
platforms).

The i915_drv.c was let out of this patch on purpose
because that is really a decision per platform, just like
other cases where IS_KABYLAKE is different from IS_SKYLAKE.

v2: fix conflict with IS_LP and 3 new cases for this
    big core bucket:
    - intel_ddi.c: intel_ddi_get_link_dpll
    - intel_fbc.c: find_compression_threshold
    - i915_gem_gtt.c: gtt_write_workarounds

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarAnder Conselvan de Oliveira <conselvan2@gmail.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1485196357-30599-2-git-send-email-rodrigo.vivi@intel.com
parent 8da53efa

drivers/gpu/drm/i915/i915_debugfs.c

+7 −10
Original line number Original line Diff line number Diff line
@@ -1224,21 +1224,18 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 




		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

			    rp_state_cap >> 16) & 0xff;

			    rp_state_cap >> 16) & 0xff;

		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?

		max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);

			     GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

			   intel_gpu_freq(dev_priv, max_freq));

			   intel_gpu_freq(dev_priv, max_freq));





		max_freq = (rp_state_cap & 0xff00) >> 8;

		max_freq = (rp_state_cap & 0xff00) >> 8;

		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?

		max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);

			     GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

			   intel_gpu_freq(dev_priv, max_freq));

			   intel_gpu_freq(dev_priv, max_freq));





		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :

		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :

			    rp_state_cap >> 0) & 0xff;

			    rp_state_cap >> 0) & 0xff;

		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?

		max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);

			     GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   intel_gpu_freq(dev_priv, max_freq));

			   intel_gpu_freq(dev_priv, max_freq));

		seq_printf(m, "Max overclocked frequency: %dMHz\n",

		seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1814,7 +1811,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 
	if (ret)

	if (ret)

		goto out;

		goto out;





	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_GEN9_BC(dev_priv)) {

		/* Convert GT frequency to 50 HZ units */

		/* Convert GT frequency to 50 HZ units */

		min_gpu_freq =

		min_gpu_freq =

			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;

			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
@@ -1834,7 +1831,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 
				       &ia_freq);

				       &ia_freq);

		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",

		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",

			   intel_gpu_freq(dev_priv, (gpu_freq *

			   intel_gpu_freq(dev_priv, (gpu_freq *

				(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?

						     (IS_GEN9_BC(dev_priv) ?

						      GEN9_FREQ_SCALER : 1))),

						      GEN9_FREQ_SCALER : 1))),

			   ((ia_freq >> 0) & 0xff) * 100,

			   ((ia_freq >> 0) & 0xff) * 100,

			   ((ia_freq >> 8) & 0xff) * 100);

			   ((ia_freq >> 8) & 0xff) * 100);
@@ -4450,7 +4447,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 




		sseu->slice_mask |= BIT(s);

		sseu->slice_mask |= BIT(s);





		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

		if (IS_GEN9_BC(dev_priv))

			sseu->subslice_mask =

			sseu->subslice_mask =

				INTEL_INFO(dev_priv)->sseu.subslice_mask;

				INTEL_INFO(dev_priv)->sseu.subslice_mask;

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -2760,8 +2760,9 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))

#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))

#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))

#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))





#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)

#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)

#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)

#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))

#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))





#define ENGINE_MASK(id)	BIT(id)

#define ENGINE_MASK(id)	BIT(id)

#define RENDER_RING	ENGINE_MASK(RCS)

#define RENDER_RING	ENGINE_MASK(RCS)

drivers/gpu/drm/i915/i915_gem_gtt.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -2189,7 +2189,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) 
		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);

	else if (IS_CHERRYVIEW(dev_priv))

	else if (IS_CHERRYVIEW(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);

	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

	else if (IS_GEN9_BC(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);

	else if (IS_BROXTON(dev_priv))

	else if (IS_BROXTON(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);

drivers/gpu/drm/i915/intel_audio.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -702,7 +702,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, 
	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);

	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);

	u32 tmp;

	u32 tmp;





	if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))

	if (!IS_GEN9_BC(dev_priv))

		return;

		return;





	i915_audio_component_get_power(kdev);

	i915_audio_component_get_power(kdev);

drivers/gpu/drm/i915/intel_color.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -536,8 +536,8 @@ void intel_color_init(struct drm_crtc *crtc) 
	} else if (IS_HASWELL(dev_priv)) {

	} else if (IS_HASWELL(dev_priv)) {

		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;

		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;

		dev_priv->display.load_luts = haswell_load_luts;

		dev_priv->display.load_luts = haswell_load_luts;

	} else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||

	} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||

		   IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {

		   IS_BROXTON(dev_priv)) {

		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;

		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;

		dev_priv->display.load_luts = broadwell_load_luts;

		dev_priv->display.load_luts = broadwell_load_luts;

	} else {

	} else {