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Commit b7b6aa75 authored by Jack Pham's avatar Jack Pham
Browse files

usb: dwc3: Add GDBGLTSSM register offset for dwc31 IP 



For DWC USB 3.1 IP, the register location for GDBGLTSSM has
moved to the link register block. Add the macro definition
for it. Revision checks needs to be added wherever the register
is read to ensure the correct offset is used.

Change-Id: I814914e51fa3a5534de93770d705728223f8d7f6
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent b2bdf7dc

drivers/usb/dwc3/core.h

+3 −0
Original line number Diff line number Diff line
@@ -159,6 +159,9 @@ 
#define DWC3_OEVTEN		0xcc0C

#define DWC3_OSTS		0xcc10



/* DWC 3.1 Link Registers */

#define DWC31_LINK_GDBGLTSSM	0xd050



/* Bit fields */



/* Global Debug Queue/FIFO Space Available Register */

drivers/usb/dwc3/dwc3-msm.c

+15 −3
Original line number Diff line number Diff line
@@ -2393,6 +2393,11 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) 
		dwc3_msm_power_collapse_por(mdwc);



		/* Get initial P3 status and enable IN_P3 event */

		if (dwc3_is_usb31(dwc))

			tmp = dwc3_msm_read_reg_field(mdwc->base,

				DWC31_LINK_GDBGLTSSM,

				DWC3_GDBGLTSSM_LINKSTATE_MASK);

		else

			tmp = dwc3_msm_read_reg_field(mdwc->base,

				DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK);

		atomic_set(&mdwc->in_p3, tmp == DWC3_LINK_STATE_U3);
@@ -2569,8 +2574,15 @@ static void dwc3_pwr_event_handler(struct dwc3_msm *mdwc) 
	/* Check for P3 events */

	if ((irq_stat & PWR_EVNT_POWERDOWN_OUT_P3_MASK) &&

			(irq_stat & PWR_EVNT_POWERDOWN_IN_P3_MASK)) {

		u32 ls;



		/* Can't tell if entered or exit P3, so check LINKSTATE */

		u32 ls = dwc3_msm_read_reg_field(mdwc->base,

		if (dwc3_is_usb31(dwc))

			ls = dwc3_msm_read_reg_field(mdwc->base,

				DWC31_LINK_GDBGLTSSM,

				DWC3_GDBGLTSSM_LINKSTATE_MASK);

		else

			ls = dwc3_msm_read_reg_field(mdwc->base,

				DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK);

		dev_dbg(mdwc->dev, "%s link state = 0x%04x\n", __func__, ls);

		atomic_set(&mdwc->in_p3, ls == DWC3_LINK_STATE_U3);