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Commit b57ee99f authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
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[ARM] 5417/1: Set the correct cacheid for ARMv6 CPUs with ARMv7 style MMU 



The cacheid_init() function assumes that if cpu_architecture() returns
7, the caches are VIPT_NONALIASING. The cpu_architecture() function
returns the version of the supported MMU features (e.g. TEX remapping)
but it doesn't make any assumptions about the cache type. The patch adds
the checking of the Cache Type Register for the ARMv7 format.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 25ef4a67

arch/arm/kernel/setup.c

+7 −6
Original line number Original line Diff line number Diff line
@@ -233,12 +233,13 @@ static void __init cacheid_init(void) 
	unsigned int cachetype = read_cpuid_cachetype();

	unsigned int cachetype = read_cpuid_cachetype();

	unsigned int arch = cpu_architecture();

	unsigned int arch = cpu_architecture();





	if (arch >= CPU_ARCH_ARMv7) {

	if (arch >= CPU_ARCH_ARMv6) {

		if ((cachetype & (7 << 29)) == 4 << 29) {

			/* ARMv7 register format */

			cacheid = CACHEID_VIPT_NONALIASING;

			cacheid = CACHEID_VIPT_NONALIASING;

			if ((cachetype & (3 << 14)) == 1 << 14)

			if ((cachetype & (3 << 14)) == 1 << 14)

				cacheid |= CACHEID_ASID_TAGGED;

				cacheid |= CACHEID_ASID_TAGGED;

	} else if (arch >= CPU_ARCH_ARMv6) {

		} else if (cachetype & (1 << 23))

		if (cachetype & (1 << 23))

			cacheid = CACHEID_VIPT_ALIASING;

			cacheid = CACHEID_VIPT_ALIASING;

		else

		else

			cacheid = CACHEID_VIPT_NONALIASING;

			cacheid = CACHEID_VIPT_NONALIASING;