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Commit b52ae50c authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "dts: sa8155-capture: Add cpus 1 to 7"

parents 3c2d6c8a e8158c0f

arch/arm64/boot/dts/qcom/sa8155-capture.dtsi

+203 −0
Original line number Diff line number Diff line
@@ -64,6 +64,209 @@ 
				qcom,dump-size = <0x5000>;

			};

		};



		CPU1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_1>;

			#cooling-cells = <0x2>;



			L2_1: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <0x2>;

				next-level-cache = <&L3_0>;

			};



			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_100: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU2: cpu@200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_2>;

			#cooling-cells = <0x2>;



			L2_2: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <0x2>;

				next-level-cache = <&L3_0>;

			};



			L1_I_200: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_200: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_200: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU3: cpu@300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_3>;

			#cooling-cells = <0x2>;



			L2_3: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <0x2>;

				next-level-cache = <&L3_0>;

			};



			L1_I_300: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_300: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_300: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU4: cpu@400 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_4>;

			#cooling-cells = <0x2>;



			L2_4: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <0x2>;

				next-level-cache = <&L3_0>;

			};



			L1_I_400: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_400: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_400: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU5: cpu@500 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_5>;

			#cooling-cells = <0x2>;



			L2_5: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <0x2>;

				next-level-cache = <&L3_0>;

			};



			L1_I_500: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_500: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_500: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU6: cpu@600 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_6>;

			#cooling-cells = <0x2>;



			L2_6: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <0x2>;

				next-level-cache = <&L3_0>;

			};



			L1_I_600: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_600: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_600: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};



		CPU7: cpu@700 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_7>;

			#cooling-cells = <0x2>;



			L2_7: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <0x2>;

				next-level-cache = <&L3_0>;

			};



			L1_I_700: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x8800>;

			};



			L1_D_700: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_700: l2-tlb {

				qcom,dump-size = <0x5000>;

			};

		};

	};



	soc: soc { } ;