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Commit aec07978 authored by Rama Aparna Mallavarapu's avatar Rama Aparna Mallavarapu
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coresight: cti: Add snapshot of Coresight CTI driver



This is a snapshot of the coresight-cti driver as of msm-4.9
commit '11b572c36aa87d0fc208892840d20cd24719a4fa'. Fix unbalanced
PM runtime calls. Vote for the CTI device to be turned off when
we reset the device in order to save power.

Change-Id: I2596a77f0df7b36c47a11800b3b922c014f81ed7
Signed-off-by: default avatarRama Aparna Mallavarapu <aparnam@codeaurora.org>
parent 0722e738
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+14 −0
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@@ -56,6 +56,8 @@ its hardware characteristcs.
	  layout using the generic DT graph presentation found in
	  layout using the generic DT graph presentation found in
	  "bindings/graph.txt".
	  "bindings/graph.txt".


	* coresight-name: unique descriptive name of the component.

* Additional required properties for System Trace Macrocells (STM):
* Additional required properties for System Trace Macrocells (STM):
	* reg: along with the physical base address and length of the register
	* reg: along with the physical base address and length of the register
	  set as described above, another entry is required to describe the
	  set as described above, another entry is required to describe the
@@ -70,9 +72,14 @@ its hardware characteristcs.
	* compatible: Currently supported value is (note the absence of the
	* compatible: Currently supported value is (note the absence of the
	  AMBA markee):
	  AMBA markee):
		- "arm,coresight-replicator"
		- "arm,coresight-replicator"
		- "arm,coresight-cti"


	* port or ports: same as above.
	* port or ports: same as above.


	* coresight-name: unique descriptive name of the component.

* Optional properties for all components:
	* reg-names: names corresponding to each reg property value.
* Optional properties for ETM/PTMs:
* Optional properties for ETM/PTMs:


	* arm,cp14: must be present if the system accesses ETM/PTM management
	* arm,cp14: must be present if the system accesses ETM/PTM management
@@ -85,7 +92,14 @@ its hardware characteristcs.


	* arm,buffer-size: size of contiguous buffer space for TMC ETR
	* arm,buffer-size: size of contiguous buffer space for TMC ETR
	 (embedded trace router)
	 (embedded trace router)
	* arm,default-sink: represents the default compile time CoreSight sink

	* coresight-ctis: represents flush and reset CTIs for TMC buffer

	* qcom,force-reg-dump: enables TMC reg dump support


	* arm,sg-enable : indicates whether scatter gather feature is enabled
	  by default for TMC ETR configuration.


Example:
Example:


+7 −0
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@@ -103,4 +103,11 @@ config CORESIGHT_CPU_DEBUG
	  properly, please refer Documentation/trace/coresight-cpu-debug.txt
	  properly, please refer Documentation/trace/coresight-cpu-debug.txt
	  for detailed description and the example for usage.
	  for detailed description and the example for usage.


config CORESIGHT_CTI
	bool "CoreSight Cross Trigger Interface driver"
	help
	  This driver provides support for Cross Trigger Interface that is
	  used to input or output i.e. pass cross trigger events from one
	  hardware component to another. It can also be used to pass
	  software generated events.
endif
endif
+1 −0
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@@ -17,3 +17,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
+1536 −0

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+2 −1
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/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
/* Copyright (c) 2011-2012, 2017, The Linux Foundation. All rights reserved.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * it under the terms of the GNU General Public License version 2 and
@@ -33,6 +33,7 @@
#define CORESIGHT_DEVTYPE	0xfcc
#define CORESIGHT_DEVTYPE	0xfcc


#define TIMEOUT_US		100
#define TIMEOUT_US		100
#define BM(lsb, msb)		((BIT(msb) - BIT(lsb)) + BIT(msb))
#define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)
#define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)


#define ETM_MODE_EXCL_KERN	BIT(30)
#define ETM_MODE_EXCL_KERN	BIT(30)
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