Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ad1c7139 authored by Anirudh Ghayal's avatar Anirudh Ghayal
Browse files

power: qpnp-qg: Add sleep-mode configuration for QG 



Add support for updating the S2 state configuration
in sleep. This allows modifying the fifo-length, accumulator
interval and accumulator length when the device enters suspend.

Change-Id: I3e51dc34cea5c97a7f901d9981f908e35b8b0fb3
Signed-off-by: default avatarAnirudh Ghayal <aghayal@codeaurora.org>
parent 1db981f0

drivers/power/supply/qcom/qg-core.h

+13 −0
Original line number Diff line number Diff line
@@ -42,6 +42,9 @@ struct qg_dt { 
	int			s2_vbat_low_fifo_length;

	int			s2_acc_length;

	int			s2_acc_intvl_ms;

	int			sleep_s2_fifo_length;

	int			sleep_s2_acc_length;

	int			sleep_s2_acc_intvl_ms;

	int			ocv_timer_expiry_min;

	int			ocv_tol_threshold_uv;

	int			s3_entry_fifo_length;
@@ -67,6 +70,7 @@ struct qg_dt { 
	bool			esr_discharge_enable;

	bool			qg_ext_sense;

	bool			use_s7_ocv;

	bool			qg_sleep_config;

};



struct qg_esr_data {
@@ -91,6 +95,7 @@ struct qpnp_qg { 
	struct work_struct	udata_work;

	struct work_struct	scale_soc_work;

	struct work_struct	qg_status_change_work;

	struct delayed_work	qg_sleep_exit_work;

	struct notifier_block	nb;

	struct mutex		bus_lock;

	struct mutex		data_lock;
@@ -141,6 +146,8 @@ struct qpnp_qg { 
	u32			charge_counter_uah;

	u32			esr_avg;

	u32			esr_last;

	u32			s2_state;

	u32			s2_state_mask;

	ktime_t			last_user_update_time;

	ktime_t			last_fifo_update_time;

	unsigned long		last_maint_soc_update_time;
@@ -187,6 +194,12 @@ enum ocv_type { 
	PON_OCV_MAX,

};



enum s2_state {

	S2_LOW_VBAT = BIT(0),

	S2_SLEEP = BIT(1),

	S2_DEFAULT = BIT(2),

};



enum debug_mask {

	QG_DEBUG_PON		= BIT(0),

	QG_DEBUG_PROFILE	= BIT(1),

drivers/power/supply/qcom/qg-defs.h

+3 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2018 The Linux Foundation. All rights reserved.

/* Copyright (c) 2018,2019 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -35,6 +35,8 @@ 
#define PROFILE_IRQ_DISABLE		"NO_PROFILE_IRQ_DISABLE"

#define QG_INIT_STATE_IRQ_DISABLE	"QG_INIT_STATE_IRQ_DISABLE"

#define TTF_AWAKE_VOTER			"TTF_AWAKE_VOTER"

#define SLEEP_EXIT_DATA_VOTER		"SLEEP_EXIT_DATA_VOTER"

#define SLEEP_EXIT_VOTER		"SLEEP_EXIT_VOTER"



#define V_RAW_TO_UV(V_RAW)		div_u64(194637ULL * (u64)V_RAW, 1000)

#define FIFO_V_RESET_VAL		0x8000

drivers/power/supply/qcom/qpnp-qg.c

+199 −37
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ module_param_named( 
	esr_count, qg_esr_count, int, 0600

);



static int qg_process_rt_fifo(struct qpnp_qg *chip);



static bool is_battery_present(struct qpnp_qg *chip)

{

	u8 reg = 0;
@@ -146,7 +148,7 @@ static int qg_update_fifo_length(struct qpnp_qg *chip, u8 length) 
		pr_err("Failed to write S2 FIFO length, rc=%d\n", rc);



	/* update the S3 FIFO length, when S2 length is updated */

	if (length > 3)

	if (length > 3 && !chip->dt.qg_sleep_config)

		s3_entry_fifo_length = (chip->dt.s3_entry_fifo_length > 0) ?

			chip->dt.s3_entry_fifo_length : DEFAULT_S3_FIFO_LENGTH;

	else	/* Use S3 length as 1 for any S2 length <= 3 */
@@ -275,6 +277,104 @@ static int qg_store_soc_params(struct qpnp_qg *chip) 
	return rc;

}



static int qg_config_s2_state(struct qpnp_qg *chip,

		enum s2_state requested_state, bool state_enable,

		bool process_fifo)

{

	int rc, acc_interval, acc_length;

	u8 fifo_length, reg = 0, state = S2_DEFAULT;



	if ((chip->s2_state_mask & requested_state) && (state_enable == true))

		return 0; /* No change in state */



	if (!(chip->s2_state_mask & requested_state) && (state_enable == false))

		return 0; /* No change in state */



	if (state_enable)

		chip->s2_state_mask |= requested_state;

	else

		chip->s2_state_mask &= ~requested_state;



	/* define the priority of the states */

	if (chip->s2_state_mask & S2_LOW_VBAT)

		state = S2_LOW_VBAT;

	else if (chip->s2_state_mask & S2_SLEEP)

		state = S2_SLEEP;

	else

		state = S2_DEFAULT;



	if (state == chip->s2_state)

		return 0;



	switch (state) {

	case S2_LOW_VBAT:

		fifo_length = chip->dt.s2_vbat_low_fifo_length;

		acc_interval = chip->dt.s2_acc_intvl_ms;

		acc_length = chip->dt.s2_acc_length;

		break;

	case S2_SLEEP:

		fifo_length = chip->dt.sleep_s2_fifo_length;

		acc_interval = chip->dt.sleep_s2_acc_intvl_ms;

		acc_length = chip->dt.sleep_s2_acc_length;

		break;

	case S2_DEFAULT:

		fifo_length = chip->dt.s2_fifo_length;

		acc_interval = chip->dt.s2_acc_intvl_ms;

		acc_length = chip->dt.s2_acc_length;

		break;

	default:

		pr_err("Invalid S2 state %d\n", state);

		return -EINVAL;

	}



	rc = qg_master_hold(chip, true);

	if (rc < 0) {

		pr_err("Failed to hold master, rc=%d\n", rc);

		return rc;

	}



	if (process_fifo) {

		rc = qg_process_rt_fifo(chip);

		if (rc < 0) {

			pr_err("Failed to process FIFO real-time, rc=%d\n", rc);

			goto done;

		}

	}



	rc = qg_update_fifo_length(chip, fifo_length);

	if (rc < 0) {

		pr_err("Failed to update S2 fifo-length, rc=%d\n", rc);

		goto done;

	}



	reg = acc_interval / 10;

	rc = qg_write(chip, chip->qg_base + QG_S2_NORMAL_MEAS_CTL3_REG,

					&reg, 1);

	if (rc < 0) {

		pr_err("Failed to update S2 acc intrvl, rc=%d\n", rc);

		goto done;

	}



	reg = ilog2(acc_length) - 1;

	rc = qg_masked_write(chip, chip->qg_base + QG_S2_NORMAL_MEAS_CTL2_REG,

					NUM_OF_ACCUM_MASK, reg);

	if (rc < 0) {

		pr_err("Failed to update S2 ACC length, rc=%d\n", rc);

		goto done;

	}



	chip->s2_state = state;



	qg_dbg(chip, QG_DEBUG_STATUS, "S2 New state=%x  fifo_length=%d interval=%d acc_length=%d\n",

				state, fifo_length, acc_interval, acc_length);



done:

	qg_master_hold(chip, false);

	/* FIFO restarted */

	chip->last_fifo_update_time = ktime_get();

	return rc;

}



static int qg_process_fifo(struct qpnp_qg *chip, u32 fifo_length)

{

	int rc = 0, i, j = 0, temp;
@@ -526,7 +626,7 @@ static int process_rt_fifo_data(struct qpnp_qg *chip, bool update_smb) 
static int qg_vbat_low_wa(struct qpnp_qg *chip)

{

	int rc, i, temp = 0;

	u32 vbat_low_uv = 0, fifo_length = 0;

	u32 vbat_low_uv = 0;



	if ((chip->wa_flags & QG_VBAT_LOW_WA) && chip->vbat_low) {

		rc = qg_get_battery_temp(chip, &temp);
@@ -556,37 +656,11 @@ static int qg_vbat_low_wa(struct qpnp_qg *chip) 
		}

	}



	rc = get_fifo_length(chip, &fifo_length, false);

	if (rc < 0) {

		pr_err("Failed to get FIFO length, rc=%d\n", rc);

		return rc;

	}



	if (chip->vbat_low && fifo_length == chip->dt.s2_vbat_low_fifo_length)

		return 0;



	if (!chip->vbat_low && fifo_length == chip->dt.s2_fifo_length)

		return 0;



	rc = qg_master_hold(chip, true);

	if (rc < 0) {

		pr_err("Failed to hold master, rc=%d\n", rc);

		goto done;

	}



	fifo_length = chip->vbat_low ? chip->dt.s2_vbat_low_fifo_length :

					chip->dt.s2_fifo_length;



	rc = qg_update_fifo_length(chip, fifo_length);

	rc = qg_config_s2_state(chip, S2_LOW_VBAT,

			chip->vbat_low ? true : false, false);

	if (rc < 0)

		goto done;

		pr_err("Failed to configure for VBAT_LOW rc=%d\n", rc);



	qg_dbg(chip, QG_DEBUG_STATUS, "FIFO length updated to %d vbat_low=%d\n",

					fifo_length, chip->vbat_low);

done:

	qg_master_hold(chip, false);

	/* FIFOs restarted */

	chip->last_fifo_update_time = ktime_get();

	return rc;

}
@@ -2275,6 +2349,33 @@ static int qg_battery_status_update(struct qpnp_qg *chip) 
	return rc;

}



static void qg_sleep_exit_work(struct work_struct *work)

{

	int rc;

	struct qpnp_qg *chip = container_of(work,

			struct qpnp_qg, qg_sleep_exit_work.work);



	vote(chip->awake_votable, SLEEP_EXIT_VOTER, true, 0);



	mutex_lock(&chip->data_lock);

	/*

	 * if this work is executing, the system has been active

	 * for a while. So, force back the S2 active configuration

	 */

	qg_dbg(chip, QG_DEBUG_STATUS, "sleep_exit_work: exit S2_SLEEP\n");

	rc = qg_config_s2_state(chip, S2_SLEEP, false, true);

	if (rc < 0)

		pr_err("Failed to exit S2_SLEEP rc=%d\n", rc);



	vote(chip->awake_votable, SLEEP_EXIT_DATA_VOTER, true, 0);

	/* signal the read thread */

	chip->data_ready = true;

	wake_up_interruptible(&chip->qg_wait_q);



	mutex_unlock(&chip->data_lock);



	vote(chip->awake_votable, SLEEP_EXIT_VOTER, false, 0);

}



static void qg_status_change_work(struct work_struct *work)

{
@@ -2449,6 +2550,7 @@ static ssize_t qg_device_read(struct file *file, char __user *buf, size_t count, 
	vote(chip->awake_votable, FIFO_DONE_VOTER, false, 0);

	vote(chip->awake_votable, FIFO_RT_DONE_VOTER, false, 0);

	vote(chip->awake_votable, SUSPEND_DATA_VOTER, false, 0);

	vote(chip->awake_votable, SLEEP_EXIT_DATA_VOTER, false, 0);



	qg_dbg(chip, QG_DEBUG_DEVICE,

		"QG device read complete Seq_no=%u Size=%ld\n",
@@ -3064,6 +3166,8 @@ static int qg_hw_init(struct qpnp_qg *chip) 
		}

	}



	chip->s2_state = S2_DEFAULT;

	chip->s2_state_mask |= S2_DEFAULT;

	/* signal the read thread */

	chip->data_ready = true;

	wake_up_interruptible(&chip->qg_wait_q);
@@ -3399,6 +3503,9 @@ static int qg_alg_init(struct qpnp_qg *chip) 
#define DEFAULT_S2_VBAT_LOW_LENGTH	2

#define DEFAULT_S2_ACC_LENGTH		128

#define DEFAULT_S2_ACC_INTVL_MS		100

#define DEFAULT_SLEEP_S2_FIFO_LENGTH	8

#define DEFAULT_SLEEP_S2_ACC_LENGTH	256

#define DEFAULT_SLEEP_S2_ACC_INTVL_MS	200

#define DEFAULT_DELTA_SOC		1

#define DEFAULT_SHUTDOWN_SOC_SECS	360

#define DEFAULT_COLD_TEMP_THRESHOLD	0
@@ -3660,6 +3767,35 @@ static int qg_parse_dt(struct qpnp_qg *chip) 
	else

		chip->dt.sys_min_volt_mv = temp;



	if (of_property_read_bool(node, "qcom,qg-sleep-config")) {



		chip->dt.qg_sleep_config = true;



		rc = of_property_read_u32(node,

				"qcom,sleep-s2-fifo-length", &temp);

		if (rc < 0)

			chip->dt.sleep_s2_fifo_length =

					DEFAULT_SLEEP_S2_FIFO_LENGTH;

		else

			chip->dt.sleep_s2_fifo_length = temp;



		rc = of_property_read_u32(node,

				"qcom,sleep-s2-acc-length", &temp);

		if (rc < 0)

			chip->dt.sleep_s2_acc_length =

					DEFAULT_SLEEP_S2_ACC_LENGTH;

		else

			chip->dt.sleep_s2_acc_length = temp;



		rc = of_property_read_u32(node,

				"qcom,sleep-s2-acc-intvl-ms", &temp);

		if (rc < 0)

			chip->dt.sleep_s2_acc_intvl_ms =

					DEFAULT_SLEEP_S2_ACC_INTVL_MS;

		else

			chip->dt.sleep_s2_acc_intvl_ms = temp;

	}



	chip->dt.qg_ext_sense = of_property_read_bool(node, "qcom,qg-ext-sns");



	chip->dt.use_s7_ocv = of_property_read_bool(node, "qcom,qg-use-s7-ocv");
@@ -3755,6 +3891,7 @@ static int process_suspend(struct qpnp_qg *chip) 
		return 0;



	cancel_delayed_work_sync(&chip->ttf->ttf_work);

	cancel_delayed_work_sync(&chip->qg_sleep_exit_work);



	chip->suspend_data = false;
@@ -3763,6 +3900,13 @@ static int process_suspend(struct qpnp_qg *chip) 


	/* ignore any suspend processing if we are charging */

	if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING) {

		/* Reset the sleep config if we are charging */

		if (chip->dt.qg_sleep_config) {

			qg_dbg(chip, QG_DEBUG_STATUS, "Suspend: Charging - Exit S2_SLEEP\n");

			rc = qg_config_s2_state(chip, S2_SLEEP, false, true);

			if (rc < 0)

				pr_err("Failed to exit S2-sleep rc=%d\n", rc);

		}

		qg_dbg(chip, QG_DEBUG_PM, "Charging @ suspend - ignore processing\n");

		return 0;

	}
@@ -3780,12 +3924,23 @@ static int process_suspend(struct qpnp_qg *chip) 
		return rc;

	}

	sleep_fifo_length &= SLEEP_IBAT_QUALIFIED_LENGTH_MASK;



	if (chip->dt.qg_sleep_config) {

		qg_dbg(chip, QG_DEBUG_STATUS, "Suspend: Forcing S2_SLEEP\n");

		rc = qg_config_s2_state(chip, S2_SLEEP, true, true);

		if (rc < 0)

			pr_err("Failed to config S2_SLEEP rc=%d\n", rc);

		if (chip->kdata.fifo_length > 0)

			chip->suspend_data = true;

	} else if (fifo_rt_length >=

			(chip->dt.s2_fifo_length - sleep_fifo_length)) {

		/*

		 * If the real-time FIFO count is greater than

		 * the the #fifo to enter sleep, save the FIFO data

	 * and reset the fifo count.

		 * and reset the fifo count. This is avoid a gauranteed wakeup

		 * due to fifo_done event as the curent FIFO length is already

		 * beyond the sleep length.

		 */

	if (fifo_rt_length >= (chip->dt.s2_fifo_length - sleep_fifo_length)) {

		rc = qg_master_hold(chip, true);

		if (rc < 0) {

			pr_err("Failed to hold master, rc=%d\n", rc);
@@ -3820,6 +3975,7 @@ static int process_suspend(struct qpnp_qg *chip) 
	return rc;

}



#define QG_SLEEP_EXIT_TIME_MS		15000 /* 15 secs */

static int process_resume(struct qpnp_qg *chip)

{

	u8 status2 = 0, rt_status = 0;
@@ -3834,6 +3990,10 @@ static int process_resume(struct qpnp_qg *chip) 
	get_rtc_time(&rtc_sec);

	sleep_time_secs = rtc_sec - chip->suspend_time;



	if (chip->dt.qg_sleep_config)

		schedule_delayed_work(&chip->qg_sleep_exit_work,

				msecs_to_jiffies(QG_SLEEP_EXIT_TIME_MS));



	rc = qg_read(chip, chip->qg_base + QG_STATUS2_REG, &status2, 1);

	if (rc < 0) {

		pr_err("Failed to read status2 register, rc=%d\n", rc);
@@ -4001,6 +4161,7 @@ static int qpnp_qg_probe(struct platform_device *pdev) 
	platform_set_drvdata(pdev, chip);

	INIT_WORK(&chip->udata_work, process_udata_work);

	INIT_WORK(&chip->qg_status_change_work, qg_status_change_work);

	INIT_DELAYED_WORK(&chip->qg_sleep_exit_work, qg_sleep_exit_work);

	mutex_init(&chip->bus_lock);

	mutex_init(&chip->soc_lock);

	mutex_init(&chip->data_lock);
@@ -4161,6 +4322,7 @@ static int qpnp_qg_remove(struct platform_device *pdev) 
	qg_batterydata_exit();

	qg_soc_exit(chip);



	cancel_delayed_work_sync(&chip->qg_sleep_exit_work);

	cancel_work_sync(&chip->udata_work);

	cancel_work_sync(&chip->qg_status_change_work);

	device_destroy(chip->qg_class, chip->dev_no);