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Commit aad6f0a0 authored by Anant Goel's avatar Anant Goel Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add syscon nodes to the sdmshrike target 



Provide an entry to invoke the syscon driver. Associate
the global clock controller, camera clock controller, and
GPU clock controller with the syscon driver for clock
measurement support.

Change-Id: I0ecf832c89a5d773c2e237b5a05e0cea52f7f515
Signed-off-by: default avatarAnant Goel <anantg@codeaurora.org>
parent 35a9a730

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+8 −3
Original line number Diff line number Diff line
@@ -1372,7 +1372,7 @@ 
	};



	clock_gcc: qcom,gcc@100000 {

		compatible = "qcom,gcc-sdmshrike";

		compatible = "qcom,gcc-sdmshrike", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -1415,7 +1415,7 @@ 
	};



	clock_camcc: qcom,camcc@ad00000 {

		compatible = "qcom,camcc-sdmshrike";

		compatible = "qcom,camcc-sdmshrike", "syscon";

		reg = <0xad00000 0x20000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&pm8150c_s3_level>;
@@ -1437,7 +1437,7 @@ 
	};



	clock_gpucc: qcom,gpucc@2c90000 {

		compatible = "qcom,gpucc-sdmshrike";

		compatible = "qcom,gpucc-sdmshrike", "syscon";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -1453,6 +1453,11 @@ 
		status = "disabled";

	};



	cpucc_debug: syscon@182a0018 {

		compatible = "syscon";

		reg = <0x182a0018 0x4>;

	};



	tsens0: tsens@c222000 {

		compatible = "qcom,tsens24xx";

		reg = <0xc222000 0x4>,