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Commit aaad018f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable dynamic dsi clk switch on atoll"

parents f22e8ff4 0acdfa41

arch/arm64/boot/dts/qcom/atoll-sde-display.dtsi

+9 −2
Original line number Diff line number Diff line
@@ -94,7 +94,9 @@ 


		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-phy-num = <0>;

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";



		qcom,dsi-panel = <&dsi_rm69299_visionox_amoled_video>;

	};
@@ -220,7 +222,9 @@ 
	qcom,dsi-supported-dfps-list = <60 55 48>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";



	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list =

		<950938560 935089584 939051832 943014072 946976320>;

	qcom,mdss-dsi-t-clk-post = <0x0E>;

	qcom,mdss-dsi-t-clk-pre = <0x31>;

	qcom,mdss-dsi-display-timings {
@@ -241,6 +245,9 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-on-check-value = <0x9c>;

	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list =

		<1034259840 1017022176 1021331592 1025641008 1029950424>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,mdss-dsi-t-clk-post = <0x0E>;

	qcom,mdss-dsi-t-clk-pre = <0x31>;

arch/arm64/boot/dts/qcom/atoll-sde-pll.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -25,7 +25,10 @@ 
		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		memory-region = <&dfps_data_memory>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

arch/arm64/boot/dts/qcom/atoll.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -619,10 +619,15 @@ 
		};



		cont_splash_memory: cont_splash_region@9bc00000 {

			reg = <0x0 0x9bc00000 0x0 0x02400000>;

			reg = <0x0 0x9bc00000 0x0 0x02300000>;

			label = "cont_splash_region";

		};



		dfps_data_memory: dfps_data_region@9df00000 {

			reg = <0x0 0x9df00000 0x0 0x0100000>;

			label = "dfps_data_region";

		};



		adsp_mem: adsp_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;