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Commit a7baac6e authored by Veera Vegivada's avatar Veera Vegivada Committed by Gerrit - the friendly Code Review server
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clk: qcom: update pll configs for npu clock controller 



Add the PLL configs for PLLs to allow reconfiguration
in the case the configurations are lost.

Change-Id: I457be7be864e4d98a03f4ac88f42669c7e1b33a1
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent 6345ce95

drivers/clk/qcom/npucc-sm8150.c

+11 −11
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -96,7 +96,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config npu_cc_pll0_config = {

static struct alpha_pll_config npu_cc_pll0_config = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -110,7 +110,7 @@ static const struct alpha_pll_config npu_cc_pll0_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config npu_cc_pll0_config_sm8150_v2 = {

static struct alpha_pll_config npu_cc_pll0_config_sm8150_v2 = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -129,6 +129,7 @@ static struct clk_alpha_pll npu_cc_pll0 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &npu_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "npu_cc_pll0",
@@ -169,7 +170,7 @@ static struct clk_alpha_pll_postdiv npu_cc_pll0_out_even = { 
	},

};



static const struct alpha_pll_config npu_cc_pll1_config = {

static struct alpha_pll_config npu_cc_pll1_config = {

	.l = 0x24,

	.alpha = 0x7555,

	.config_ctl_val = 0x20485699,
@@ -183,7 +184,7 @@ static const struct alpha_pll_config npu_cc_pll1_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config npu_cc_pll1_config_sm8150_v2 = {

static struct alpha_pll_config npu_cc_pll1_config_sm8150_v2 = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -202,6 +203,7 @@ static struct clk_alpha_pll npu_cc_pll1 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &npu_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "npu_cc_pll1",
@@ -661,10 +663,8 @@ MODULE_DEVICE_TABLE(of, npu_cc_sm8150_match_table); 


static void npu_cc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&npu_cc_pll0, regmap,

		&npu_cc_pll0_config_sm8150_v2);

	clk_trion_pll_configure(&npu_cc_pll1, regmap,

		&npu_cc_pll1_config_sm8150_v2);

	npu_cc_pll0.config = &npu_cc_pll0_config_sm8150_v2;

	npu_cc_pll1.config = &npu_cc_pll1_config_sm8150_v2;

	npu_cc_cal_dp_clk_src.freq_tbl = ftbl_npu_cc_cal_dp_clk_src_sm8150_v2;

	npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_MIN] = 0;

	npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 400000000;
@@ -759,8 +759,8 @@ static int npu_cc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&npu_cc_pll0, regmap, &npu_cc_pll0_config);

	clk_trion_pll_configure(&npu_cc_pll1, regmap, &npu_cc_pll1_config);

	clk_trion_pll_configure(&npu_cc_pll0, regmap, npu_cc_pll0.config);

	clk_trion_pll_configure(&npu_cc_pll1, regmap, npu_cc_pll1.config);



	/* Register the fixed factor clock for CRC divide */

	ret = devm_clk_hw_register(&pdev->dev, &npu_cc_crc_div.hw);