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Commit a5238e36 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
Browse files

spi: s3c64xx: move controller information into driver data 



Platform data is used to specify controller hardware specific information
such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
information is not suitable to be supplied from device tree. Instead,
it can be moved into the driver data and removed from platform data.

Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Acked-by: default avatarJaswinder Singh <jaswinder.singh@linaro.org>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 2b54be66

arch/arm/mach-exynos/clock-exynos4.c

+9 −9
Original line number Original line Diff line number Diff line
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = { 
		.ctrlbit	= (1 << 13),

		.ctrlbit	= (1 << 13),

	}, {

	}, {

		.name		= "spi",

		.name		= "spi",

		.devname	= "s3c64xx-spi.0",

		.devname	= "exynos4210-spi.0",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 16),

		.ctrlbit	= (1 << 16),

	}, {

	}, {

		.name		= "spi",

		.name		= "spi",

		.devname	= "s3c64xx-spi.1",

		.devname	= "exynos4210-spi.1",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 17),

		.ctrlbit	= (1 << 17),

	}, {

	}, {

		.name		= "spi",

		.name		= "spi",

		.devname	= "s3c64xx-spi.2",

		.devname	= "exynos4210-spi.2",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 18),

		.ctrlbit	= (1 << 18),

	}, {

	}, {
@@ -1245,7 +1245,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { 
static struct clksrc_clk exynos4_clk_sclk_spi0 = {

static struct clksrc_clk exynos4_clk_sclk_spi0 = {

	.clk	= {

	.clk	= {

		.name		= "sclk_spi",

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.0",

		.devname	= "exynos4210-spi.0",

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit	= (1 << 16),

		.ctrlbit	= (1 << 16),

	},

	},
@@ -1257,7 +1257,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = { 
static struct clksrc_clk exynos4_clk_sclk_spi1 = {

static struct clksrc_clk exynos4_clk_sclk_spi1 = {

	.clk	= {

	.clk	= {

		.name		= "sclk_spi",

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.1",

		.devname	= "exynos4210-spi.1",

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit	= (1 << 20),

		.ctrlbit	= (1 << 20),

	},

	},
@@ -1269,7 +1269,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = { 
static struct clksrc_clk exynos4_clk_sclk_spi2 = {

static struct clksrc_clk exynos4_clk_sclk_spi2 = {

	.clk	= {

	.clk	= {

		.name		= "sclk_spi",

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.2",

		.devname	= "exynos4210-spi.2",

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit	= (1 << 24),

		.ctrlbit	= (1 << 24),

	},

	},
@@ -1347,9 +1347,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { 
	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),

	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),

	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),

	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),

	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),

	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),

	CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),

	CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),

	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),

	CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),

};

};





static int xtal_rate;

static int xtal_rate;

arch/arm/mach-exynos/setup-spi.c

+0 −25
Original line number Original line Diff line number Diff line
@@ -12,17 +12,8 @@ 
#include <linux/platform_device.h>

#include <linux/platform_device.h>





#include <plat/gpio-cfg.h>

#include <plat/gpio-cfg.h>

#include <plat/s3c64xx-spi.h>





#ifdef CONFIG_S3C64XX_DEV_SPI0

#ifdef CONFIG_S3C64XX_DEV_SPI0

struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {

	.fifo_lvl_mask	= 0x1ff,

	.rx_lvl_offset	= 15,

	.high_speed	= 1,

	.clk_from_cmu	= true,

	.tx_st_done	= 25,

};



int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)

int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)

{

{

	s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));

	s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
@@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) 
#endif

#endif





#ifdef CONFIG_S3C64XX_DEV_SPI1

#ifdef CONFIG_S3C64XX_DEV_SPI1

struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {

	.fifo_lvl_mask	= 0x7f,

	.rx_lvl_offset	= 15,

	.high_speed	= 1,

	.clk_from_cmu	= true,

	.tx_st_done	= 25,

};



int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)

int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)

{

{

	s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));

	s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
@@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) 
#endif

#endif





#ifdef CONFIG_S3C64XX_DEV_SPI2

#ifdef CONFIG_S3C64XX_DEV_SPI2

struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {

	.fifo_lvl_mask	= 0x7f,

	.rx_lvl_offset	= 15,

	.high_speed	= 1,

	.clk_from_cmu	= true,

	.tx_st_done	= 25,

};



int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)

int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)

{

{

	s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));

	s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));

arch/arm/mach-s3c24xx/clock-s3c2416.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = { 
	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),

	/* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */

	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),

};

};





void __init s3c2416_init_clocks(int xtal)

void __init s3c2416_init_clocks(int xtal)

arch/arm/mach-s3c24xx/clock-s3c2443.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = { 




static struct clk_lookup s3c2443_clk_lookup[] = {

static struct clk_lookup s3c2443_clk_lookup[] = {

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),

	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),

};

};





void __init s3c2443_init_clocks(int xtal)

void __init s3c2443_init_clocks(int xtal)

arch/arm/mach-s3c24xx/common-s3c2443.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = { 




static struct clk hsspi_clk = {

static struct clk hsspi_clk = {

	.name		= "spi",

	.name		= "spi",

	.devname	= "s3c64xx-spi.0",

	.devname	= "s3c2443-spi.0",

	.parent		= &clk_p,

	.parent		= &clk_p,

	.enable		= s3c2443_clkcon_enable_p,

	.enable		= s3c2443_clkcon_enable_p,

	.ctrlbit	= S3C2443_PCLKCON_HSSPI,

	.ctrlbit	= S3C2443_PCLKCON_HSSPI,
@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = { 
	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),

	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),

};

};





void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,

void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,