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Commit 9e4d4d7a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: ipa: Add support for auto"

parents bcf41eb9 84fc4ca8

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+481 −0
Original line number Diff line number Diff line
@@ -419,6 +419,32 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {

		{22, 22}, {16, 16}, {6, 6}, {2, 2}, {0, 0}, {0, 0} },

	},

	[IPA_4_5_AUTO] = {

		/* unused  UL_DL  DMA/CV2X  unused  UC_RX_Q N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{0, 0}, {1, 11}, {1, 1}, {0, 0}, {1, 63}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {

		{0, 0}, {14, 14}, {2, 2}, {0, 0}, {3, 3}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {

		{0, 0}, {18, 18}, {4, 4}, {0, 0}, {8, 8}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {

		{0, 63}, {0, 63}, {0, 63}, {0, 63},  {0, 63}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {

		{0, 0}, {24, 24}, {6, 6}, {0, 0}, {8, 8}, {0, 0} },

	},

	[IPA_4_5_AUTO_MHI] = {

		/* PCIE  DDR  DMA/CV2X  QDSS  unused  N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{3, 8}, {4, 11}, {1, 1}, {1, 1}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {

		{9, 9}, {12, 12}, {2, 2}, {2, 2}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {

		{9, 9}, {14, 14}, {4, 4}, {4, 4}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {

		{0, 63}, {0, 63}, {0, 63}, {0, 63},  {0, 63}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {

		{22, 22}, {16, 16}, {6, 6}, {2, 2}, {0, 0}, {0, 0} },

	},

};



static const struct rsrc_min_max ipa3_rsrc_dst_grp_config
@@ -502,6 +528,20 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config 
		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{2, 63}, {1, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} },

	},

	[IPA_4_5_AUTO] = {

		/* unused  UL/DL/DPL DMA/CV2X  unused  uC  N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {

		{0, 0}, {16, 16}, {2, 2}, {2, 2}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{0, 0}, {2, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} },

	},

	[IPA_4_5_AUTO_MHI] = {

		/* PCIE/DPL  DDR  DMA/CV2X  QDSS  uC  N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {

		{16, 16}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{2, 63}, {1, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} },

	},

};



static const struct rsrc_min_max ipa3_rsrc_rx_grp_config
@@ -561,6 +601,16 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config 
		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{ 3, 3 }, {3, 3}, {3, 3}, {3, 3}, {0, 0}, { 0, 0 } },

	},

	[IPA_4_5_AUTO] = {

		/* unused  UL_DL DMA/CV2X  unused  UC_RX_Q  N/A */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{0, 0}, {3, 3}, {3, 3}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5_AUTO_MHI] = {

		/* PCIE  DDR  DMA  QDSS  unused  N/A */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{ 3, 3 }, {3, 3}, {3, 3}, {3, 3}, {0, 0}, { 0, 0 } },

	},



};
@@ -643,6 +693,10 @@ static const struct ipa_qmb_outstanding ipa3_qmb_outstanding 
	[IPA_4_5][IPA_QMB_INSTANCE_PCIE]	= {12, 8},

	[IPA_4_5_MHI][IPA_QMB_INSTANCE_DDR]	= {16, 8},

	[IPA_4_5_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 8},

	[IPA_4_5_AUTO][IPA_QMB_INSTANCE_DDR]	= {16, 8},

	[IPA_4_5_AUTO][IPA_QMB_INSTANCE_PCIE]	= {12, 8},

	[IPA_4_5_AUTO_MHI][IPA_QMB_INSTANCE_DDR]	= {16, 8},

	[IPA_4_5_AUTO_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 8},

};



struct ipa_ep_configuration {
@@ -2616,6 +2670,433 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 
			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 31, 31, 8, 8, IPA_EE_AP } },



	/* IPA_4_5_AUTO */

	[IPA_4_5_AUTO][IPA_CLIENT_WLAN2_PROD]          = {

			false, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 9, 12, 8, 16, IPA_EE_AP, GSI_FREE_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO][IPA_CLIENT_USB_PROD]            = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_APPS_LAN_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 11, 14, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO][IPA_CLIENT_APPS_WAN_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } },

	[IPA_4_5_AUTO][IPA_CLIENT_APPS_CMD_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 7, 9, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_USB2_PROD]            = {

			true, IPA_v4_5_GROUP_CV2X,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO][IPA_CLIENT_ETHERNET_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_WAN_PROD]         = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_CMD_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_CV2X_PROD] = {

			true, IPA_v4_5_GROUP_CV2X,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 4, 8, 4, 8, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO][IPA_CLIENT_AQC_ETHERNET_PROD] = {

			false, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 10, 13, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },

	/* Only for test purpose */

	[IPA_4_5_AUTO][IPA_CLIENT_TEST_PROD]           = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 8, 16, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST1_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 8, 16, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST2_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 3, 5, 8, 16, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST3_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 9, 12, 8, 16, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST4_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 11, 14, 8, 16, IPA_EE_AP } },



	[IPA_4_5_AUTO][IPA_CLIENT_WLAN2_CONS]          = {

			false, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 24, 18, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO][IPA_CLIENT_USB_CONS]            = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 26, 17, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_USB_DPL_CONS]        = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 15, 15, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_ODL_DPL_CONS]        = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 22, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_APPS_LAN_CONS]       = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 16, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_APPS_WAN_CONS]       = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO][IPA_CLIENT_USB2_CONS]        = {

			true, IPA_v4_5_GROUP_CV2X,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO][IPA_CLIENT_ETHERNET_CONS]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 28, 1, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_LAN_CONS]         = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_CV2X_CONS]         = {

			true, IPA_v4_5_GROUP_CV2X,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_WAN_CONS]         = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_UL_NLO_ACK_CONS]  = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO][IPA_CLIENT_AQC_ETHERNET_CONS] = {

			false, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 23, 17, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	/* Only for test purpose */

	/* MBIM aggregation test pipes should have the same QMB as USB_CONS */

	[IPA_4_5_AUTO][IPA_CLIENT_TEST_CONS]           = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 1, 9, 9, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST1_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 1, 9, 9, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST2_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 24, 3, 8, 14, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST3_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 26, 17, 9, 9, IPA_EE_AP } },

	[IPA_4_5_AUTO][IPA_CLIENT_TEST4_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 27, 18, 9, 9, IPA_EE_AP } },

	/* Dummy consumer (pipe 31) is used in L2TP rt rule */

	[IPA_4_5_AUTO][IPA_CLIENT_DUMMY_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 31, 31, 8, 8, IPA_EE_AP } },



	/* IPA_4_5_AUTO_MHI */

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_CMD_PROD]		= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 7, 9, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_LAN_PROD]	  = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 11, 14, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_WAN_PROD]	  = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI2_PROD]            = {

			true, IPA_v4_5_GROUP_CV2X,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_PCIE,

			{ 3, 5, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_CV2X_PROD] = {

			true, IPA_v4_5_GROUP_CV2X,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 4, 8, 10, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_ETHERNET_PROD]	  = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_WAN_PROD]		= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_CMD_PROD]		= {

			true, IPA_v4_5_MHI_GROUP_PCIE,

			false,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 6, 1, 20, 24, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_DL_NLO_DATA_PROD]	= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_AUDIO_DMA_MHI_PROD]	= {

			true, IPA_v4_5_MHI_GROUP_DMA,

			false,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 4, 8, 8, 16, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 3 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI_PROD]		= {

			true, IPA_v4_5_MHI_GROUP_PCIE,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_PCIE,

			{ 1, 0, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 7 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD]	= {

			true, IPA_v4_5_MHI_GROUP_DMA,

			false,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 9, 12, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD]	= {

			true, IPA_v4_5_MHI_GROUP_DMA,

			false,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 10, 13, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	/* Only for test purpose */

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_TEST_PROD]           = {

			true, QMB_MASTER_SELECT_DDR,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 8, 16, IPA_EE_AP } },



	[IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_LAN_CONS]		= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 16, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_APPS_WAN_CONS]		= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 25, 16, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_ETHERNET_CONS]	  = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 28, 1, 9, 9, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_USB_DPL_CONS]        = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 15, 15, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_LAN_CONS]		= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_CV2X_CONS]         = {

			true, IPA_v4_5_GROUP_CV2X,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_PCIE,

			{ 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI2_CONS]        = {

			true, IPA_v4_5_GROUP_CV2X,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_PCIE,

			{ 30, 6, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_WAN_CONS]		= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_UL_NLO_DATA_CONS]	= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_UL_NLO_ACK_CONS]	= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_QBAP_STATUS_CONS]	= {

			true, IPA_v4_5_MHI_GROUP_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_Q6_AUDIO_DMA_MHI_CONS]	= {

			true, IPA_v4_5_MHI_GROUP_DMA,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_PCIE,

			{ 29, 9, 9, 9, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS]	= {

			true, IPA_v4_5_MHI_GROUP_DMA,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_PCIE,

			{ 23, 17, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS]	= {

			true, IPA_v4_5_MHI_GROUP_DMA,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_PCIE,

			{ 24, 18, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI_CONS]		= {

			true, IPA_v4_5_MHI_GROUP_PCIE,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_PCIE,

			{ 14, 1, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_MHI_DPL_CONS]		= {

			true, IPA_v4_5_MHI_GROUP_PCIE,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_PCIE,

			{ 22, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },



	/* Dummy consumer (pipe 31) is used in L2TP rt rule */

	[IPA_4_5_AUTO_MHI][IPA_CLIENT_DUMMY_CONS]          = {

			true, QMB_MASTER_SELECT_DDR,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 31, 31, 8, 8, IPA_EE_AP } },

};



static struct ipa3_mem_partition ipa_4_1_mem_part = {