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Commit 9705596d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "One build fix for an Amlogic clk driver and a handful of Allwinner clk
  driver fixes for some DT bindings and a randconfig build error that
  all came in this merge window"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: meson: gxbb: fix build error without RESET_CONTROLLER
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
parents 865be780 949bdfed

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+4 −3
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ Required properties : 
- #clock-cells : must contain 1

- #reset-cells : must contain 1



For the PRCM CCUs on H3/A64, one more clock is needed:

For the PRCM CCUs on H3/A64, two more clocks are needed:

- "pll-periph": the SoC's peripheral PLL from the main CCU

- "iosc": the SoC's internal frequency oscillator



Example for generic CCU:
@@ -39,8 +40,8 @@ Example for PRCM CCU: 
r_ccu: clock@01f01400 {

	compatible = "allwinner,sun50i-a64-r-ccu";

	reg = <0x01f01400 0x100>;

	clocks = <&osc24M>, <&osc32k>, <&iosc>;

	clock-names = "hosc", "losc", "iosc";

	clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;

	clock-names = "hosc", "losc", "iosc", "pll-periph";

	#clock-cells = <1>;

	#reset-cells = <1>;

};

drivers/clk/meson/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ config COMMON_CLK_MESON8B 
config COMMON_CLK_GXBB

	bool

	depends on COMMON_CLK_AMLOGIC

	select RESET_CONTROLLER

	help

	  Support for the clock controller on AmLogic S905 devices, aka gxbb.

	  Say Y if you want peripherals and CPU frequency scaling to work.

drivers/clk/sunxi-ng/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ config SUN8I_R_CCU 
	bool "Support for Allwinner SoCs' PRCM CCUs"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_GATE

	select SUNXI_CCU_MP

	default MACH_SUN8I || (ARCH_SUNXI && ARM64)



endif

drivers/clk/sunxi-ng/ccu-sun50i-a64.h

+3 −1
Original line number Diff line number Diff line
@@ -31,7 +31,9 @@ 
#define CLK_PLL_VIDEO0_2X		8

#define CLK_PLL_VE			9

#define CLK_PLL_DDR0			10

#define CLK_PLL_PERIPH0			11



/* PLL_PERIPH0 exported for PRCM */



#define CLK_PLL_PERIPH0_2X		12

#define CLK_PLL_PERIPH1			13

#define CLK_PLL_PERIPH1_2X		14

drivers/clk/sunxi-ng/ccu-sun5i.c

+1 −1
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb", 
static SUNXI_CCU_GATE(ahb_dma_clk,	"ahb-dma",	"ahb",

		      0x060, BIT(6), 0);

static SUNXI_CCU_GATE(ahb_bist_clk,	"ahb-bist",	"ahb",

		      0x060, BIT(6), 0);

		      0x060, BIT(7), 0);

static SUNXI_CCU_GATE(ahb_mmc0_clk,	"ahb-mmc0",	"ahb",

		      0x060, BIT(8), 0);

static SUNXI_CCU_GATE(ahb_mmc1_clk,	"ahb-mmc1",	"ahb",