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Commit 96ed1fe5 authored by Michael Neuling's avatar Michael Neuling Committed by Michael Ellerman
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powerpc/mm/radix: Invalidate ERAT on tlbiel for POWER9 DD1



On POWER9 DD1, when we do a local TLB invalidate we also need to explicitly
invalidate the ERAT.

Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent c0a36013
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+1 −0
Original line number Original line Diff line number Diff line
@@ -460,5 +460,6 @@


#define PPC_SLBIA(IH)	stringify_in_c(.long PPC_INST_SLBIA | \
#define PPC_SLBIA(IH)	stringify_in_c(.long PPC_INST_SLBIA | \
				       ((IH & 0x7) << 21))
				       ((IH & 0x7) << 21))
#define PPC_INVALIDATE_ERAT	PPC_SLBIA(7)


#endif /* _ASM_POWERPC_PPC_OPCODE_H */
#endif /* _ASM_POWERPC_PPC_OPCODE_H */
+4 −0
Original line number Original line Diff line number Diff line
@@ -50,6 +50,8 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
		__tlbiel_pid(pid, set, ric);
		__tlbiel_pid(pid, set, ric);
	}
	}
	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
	return;
	return;
}
}


@@ -83,6 +85,8 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("ptesync": : :"memory");
	asm volatile("ptesync": : :"memory");
	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
}
}


static inline void _tlbie_va(unsigned long va, unsigned long pid,
static inline void _tlbie_va(unsigned long va, unsigned long pid,