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Commit 932e9822 authored by Abhilash Kesavan's avatar Abhilash Kesavan Committed by Sylwester Nawrocki
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clk: samsung: exynos7: add gate clock for ADC block 



Add clock support for the ADC interface in Exynos7.

Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 2ab2dfe5

drivers/clk/samsung/clk-exynos7.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -486,6 +486,8 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 
		ENABLE_PCLK_PERIC0, 14, 0, 0),

		ENABLE_PCLK_PERIC0, 14, 0, 0),

	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",

	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 16, 0, 0),

		ENABLE_PCLK_PERIC0, 16, 0, 0),

	GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 20, 0, 0),

	GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",

	GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",

		ENABLE_PCLK_PERIC0, 21, 0, 0),

		ENABLE_PCLK_PERIC0, 21, 0, 0),

include/dt-bindings/clock/exynos7-clk.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -55,7 +55,8 @@ 
#define PCLK_HSI2C11			9

#define PCLK_HSI2C11			9

#define PCLK_PWM			10

#define PCLK_PWM			10

#define SCLK_PWM			11

#define SCLK_PWM			11

#define PERIC0_NR_CLK			12

#define PCLK_ADCIF			12

#define PERIC0_NR_CLK			13





/* PERIC1 */

/* PERIC1 */

#define PCLK_UART1			1

#define PCLK_UART1			1