Merge "clk: qcom: mdss: add support for dynamic refresh on DSI 14nm PLL" (8ee8bf7f) · Commits · e / devices / android_kernel_xiaomi_sm6125

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c

+9 −3

Original line number	Diff line number	Diff line
		@@ -45,9 +45,9 @@ static int mdss_pll_read_stored_trim_codes(
		struct dfps_codes_info *codes_info =
		&dsi_pll_res->dfps->codes_dfps[i];

		pr_debug("valid=%d frame_rate=%d, code %d %d\n",
		codes_info->is_valid,
		codes_info->clk_rate, codes_info->pll_codes.pll_codes_1,
		pr_debug("valid=%d, vco_rate=%d, code %d %d\n",
		codes_info->is_valid, codes_info->clk_rate,
		codes_info->pll_codes.pll_codes_1,
		codes_info->pll_codes.pll_codes_2);

		if (vco_clk_rate != codes_info->clk_rate &&
		@@ -953,7 +953,13 @@ static void shadow_pll_dynamic_refresh_14nm(struct mdss_pll_resources *pll,
		struct dsi_pll_db *pdb)
		{
		struct dsi_pll_output *pout = &pdb->out;
		u32 data = 0;

		data = (pout->pll_n1div \| (pout->pll_n2div << 4));
		MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
		DSI_DYNAMIC_REFRESH_PLL_CTRL19,
		DSIPHY_CMN_CLK_CFG0, DSIPHY_CMN_CLK_CFG1,
		data, 1);
		MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
		DSI_DYNAMIC_REFRESH_PLL_CTRL20,
		DSIPHY_CMN_CTRL_0, DSIPHY_PLL_SYSCLK_EN_RESET,

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c

+9 −5

Original line number	Diff line number	Diff line
		/* Copyright (c) 2015-2016,2018, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2015-2016,2018-2019, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -324,7 +324,8 @@ static struct clk_regmap_mux dsi0pll_pixel_clk_mux = {
		(const char *[]){ "dsi0pll_pixel_clk_src",
		"dsi0pll_shadow_pixel_clk_src"},
		.num_parents = 2,
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT),
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT \|
		CLK_SET_RATE_NO_REPARENT),
		.ops = &clk_regmap_mux_closest_ops,
		},
		},
		@@ -342,7 +343,8 @@ static struct clk_regmap_mux dsi1pll_pixel_clk_mux = {
		(const char *[]){ "dsi1pll_pixel_clk_src",
		"dsi1pll_shadow_pixel_clk_src"},
		.num_parents = 2,
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT),
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT \|
		CLK_SET_RATE_NO_REPARENT),
		.ops = &clk_regmap_mux_closest_ops,
		},
		},
		@@ -415,7 +417,8 @@ static struct clk_regmap_mux dsi0pll_byte_clk_mux = {
		"dsi0pll_shadow_byte_clk_src"},
		.num_parents = 2,
		.ops = &clk_regmap_mux_closest_ops,
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT),
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT \|
		CLK_SET_RATE_NO_REPARENT),
		},
		},
		};
		@@ -433,7 +436,8 @@ static struct clk_regmap_mux dsi1pll_byte_clk_mux = {
		"dsi1pll_shadow_byte_clk_src"},
		.num_parents = 2,
		.ops = &clk_regmap_mux_closest_ops,
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT),
		.flags = (CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT \|
		CLK_SET_RATE_NO_REPARENT),
		},
		},
		};