Loading drivers/bus/mhi/core/mhi_boot.c +15 −12 Original line number Diff line number Diff line Loading @@ -46,13 +46,14 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, MHI_LOG("BHIe programming for RDDM\n"); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS, upper_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS, lower_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len); mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len); sequence_id = prandom_u32() & BHIE_RXVECSTATUS_SEQNUM_BMSK; if (unlikely(!sequence_id)) Loading Loading @@ -122,7 +123,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) /* Hardware reset; force device to enter rddm */ MHI_LOG( "Did not enter RDDM, do a host req. reset\n"); mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, MHI_SOC_RESET_REQ); udelay(delayus); Loading Loading @@ -198,13 +199,14 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, MHI_LOG("Starting BHIe Programming\n"); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS, upper_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS, lower_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len); mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len); mhi_cntrl->sequence_id = prandom_u32() & BHIE_TXVECSTATUS_SEQNUM_BMSK; mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS, Loading Loading @@ -262,14 +264,15 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, goto invalid_pm_state; } mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH, mhi_cntrl->write_reg(mhi_cntrl, base, BHI_STATUS, 0); mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH, upper_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW, mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW, lower_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size); mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGSIZE, size); mhi_cntrl->session_id = prandom_u32() & BHI_TXDB_SEQNUM_BMSK; mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, mhi_cntrl->session_id); mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGTXDB, mhi_cntrl->session_id); read_unlock_bh(pm_lock); MHI_LOG("Waiting for image transfer completion\n"); Loading drivers/bus/mhi/core/mhi_init.c +5 −3 Original line number Diff line number Diff line Loading @@ -734,7 +734,7 @@ static int mhi_init_bw_scale(struct mhi_controller *mhi_cntrl) MHI_LOG("BW_CFG OFFSET:0x%x\n", bw_cfg_offset); /* advertise host support */ mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset, mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset, MHI_BW_SCALE_SETUP(er_index)); return 0; Loading Loading @@ -832,8 +832,8 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) /* setup wake db */ mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); mhi_cntrl->wake_set = false; /* setup bw scale db */ Loading Loading @@ -1439,6 +1439,8 @@ int of_register_mhi_controller(struct mhi_controller *mhi_cntrl) mhi_cntrl->unmap_single = mhi_unmap_single_no_bb; } mhi_cntrl->write_reg = mhi_write_reg; /* read the device info if possible */ if (mhi_cntrl->regs) { ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, Loading drivers/bus/mhi/core/mhi_main.c +4 −4 Original line number Diff line number Diff line Loading @@ -124,15 +124,15 @@ void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, tmp &= ~mask; tmp |= (val << shift); mhi_write_reg(mhi_cntrl, base, offset, tmp); mhi_cntrl->write_reg(mhi_cntrl, base, offset, tmp); } void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, dma_addr_t wp) { mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(wp)); mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(wp)); mhi_cntrl->write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(wp)); mhi_cntrl->write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(wp)); } void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, Loading Loading @@ -1489,7 +1489,7 @@ int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, read_lock_bh(&mhi_cntrl->pm_lock); if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) mhi_write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, MHI_BW_SCALE_RESULT(result, link_info.sequence_num)); Loading drivers/bus/mhi/core/mhi_pm.c +2 −2 Original line number Diff line number Diff line Loading @@ -598,7 +598,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, * device cleares INTVEC as part of RESET processing, * re-program it */ mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); } MHI_LOG("Waiting for all pending event ring processing to complete\n"); Loading Loading @@ -898,7 +898,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) mhi_cntrl->bhie = mhi_cntrl->regs + val; } mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); mhi_cntrl->pm_state = MHI_PM_POR; mhi_cntrl->ee = MHI_EE_MAX; current_ee = mhi_get_exec_env(mhi_cntrl); Loading include/linux/mhi.h +2 −0 Original line number Diff line number Diff line Loading @@ -313,6 +313,8 @@ struct mhi_controller { void (*tsync_log)(struct mhi_controller *mhi_cntrl, u64 remote_time); int (*bw_scale)(struct mhi_controller *mhi_cntrl, struct mhi_link_info *link_info); void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 val); /* channel to control DTR messaging */ struct mhi_device *dtr_dev; Loading Loading
drivers/bus/mhi/core/mhi_boot.c +15 −12 Original line number Diff line number Diff line Loading @@ -46,13 +46,14 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, MHI_LOG("BHIe programming for RDDM\n"); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS, upper_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS, lower_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len); mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len); sequence_id = prandom_u32() & BHIE_RXVECSTATUS_SEQNUM_BMSK; if (unlikely(!sequence_id)) Loading Loading @@ -122,7 +123,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) /* Hardware reset; force device to enter rddm */ MHI_LOG( "Did not enter RDDM, do a host req. reset\n"); mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, MHI_SOC_RESET_REQ); udelay(delayus); Loading Loading @@ -198,13 +199,14 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, MHI_LOG("Starting BHIe Programming\n"); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS, upper_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS, mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS, lower_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len); mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len); mhi_cntrl->sequence_id = prandom_u32() & BHIE_TXVECSTATUS_SEQNUM_BMSK; mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS, Loading Loading @@ -262,14 +264,15 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, goto invalid_pm_state; } mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH, mhi_cntrl->write_reg(mhi_cntrl, base, BHI_STATUS, 0); mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH, upper_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW, mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW, lower_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size); mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGSIZE, size); mhi_cntrl->session_id = prandom_u32() & BHI_TXDB_SEQNUM_BMSK; mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, mhi_cntrl->session_id); mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGTXDB, mhi_cntrl->session_id); read_unlock_bh(pm_lock); MHI_LOG("Waiting for image transfer completion\n"); Loading
drivers/bus/mhi/core/mhi_init.c +5 −3 Original line number Diff line number Diff line Loading @@ -734,7 +734,7 @@ static int mhi_init_bw_scale(struct mhi_controller *mhi_cntrl) MHI_LOG("BW_CFG OFFSET:0x%x\n", bw_cfg_offset); /* advertise host support */ mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset, mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset, MHI_BW_SCALE_SETUP(er_index)); return 0; Loading Loading @@ -832,8 +832,8 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) /* setup wake db */ mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); mhi_cntrl->wake_set = false; /* setup bw scale db */ Loading Loading @@ -1439,6 +1439,8 @@ int of_register_mhi_controller(struct mhi_controller *mhi_cntrl) mhi_cntrl->unmap_single = mhi_unmap_single_no_bb; } mhi_cntrl->write_reg = mhi_write_reg; /* read the device info if possible */ if (mhi_cntrl->regs) { ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, Loading
drivers/bus/mhi/core/mhi_main.c +4 −4 Original line number Diff line number Diff line Loading @@ -124,15 +124,15 @@ void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, tmp &= ~mask; tmp |= (val << shift); mhi_write_reg(mhi_cntrl, base, offset, tmp); mhi_cntrl->write_reg(mhi_cntrl, base, offset, tmp); } void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, dma_addr_t wp) { mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(wp)); mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(wp)); mhi_cntrl->write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(wp)); mhi_cntrl->write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(wp)); } void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, Loading Loading @@ -1489,7 +1489,7 @@ int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, read_lock_bh(&mhi_cntrl->pm_lock); if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) mhi_write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, MHI_BW_SCALE_RESULT(result, link_info.sequence_num)); Loading
drivers/bus/mhi/core/mhi_pm.c +2 −2 Original line number Diff line number Diff line Loading @@ -598,7 +598,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, * device cleares INTVEC as part of RESET processing, * re-program it */ mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); } MHI_LOG("Waiting for all pending event ring processing to complete\n"); Loading Loading @@ -898,7 +898,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) mhi_cntrl->bhie = mhi_cntrl->regs + val; } mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); mhi_cntrl->pm_state = MHI_PM_POR; mhi_cntrl->ee = MHI_EE_MAX; current_ee = mhi_get_exec_env(mhi_cntrl); Loading
include/linux/mhi.h +2 −0 Original line number Diff line number Diff line Loading @@ -313,6 +313,8 @@ struct mhi_controller { void (*tsync_log)(struct mhi_controller *mhi_cntrl, u64 remote_time); int (*bw_scale)(struct mhi_controller *mhi_cntrl, struct mhi_link_info *link_info); void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 val); /* channel to control DTR messaging */ struct mhi_device *dtr_dev; Loading