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Commit 8c48f981 authored by Nitesh Gupta's avatar Nitesh Gupta Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add PCIe reset support for QCS405 



BCR reset will do the group or block reset associated to the clock domain.
Add PCIe Block reset and PHY reset support for QCS405.

Change-Id: I770d3c9cc613c5d452f4bb082c21e955287326a5
Signed-off-by: default avatarNitesh Gupta <nitegupt@codeaurora.org>
parent be1961a6

arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi

+9 −3
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -116,8 +116,14 @@ 
						<0>, <0>, <0>, <0>;



		clock-output-names = "pcie_0_pipe_clk";

		resets = <&clock_gcc GCC_PCIEPHY_0_PHY_BCR>;

		reset-names = "pcie_0_phy_reset";



		resets = <&clock_gcc GCC_PCIEPHY_0_PHY_BCR>,

			<&clock_gcc GCC_PCIE_0_BCR>,

			<&clock_gcc GCC_PCIE_0_PHY_BCR>;



		reset-names = "pcie_0_phy_reset",

				"pcie_0_core_reset",

				"pcie_phy_reset";



		pcie_rc0: pcie_rc0 {

			#address-cells = <5>;