Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 88f7de35 authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: Add LMH-DCVSh configuration for ATOLL 



Add LMH-DCVSh hardware configuration like debug interrupt and cluster
affinity value for SDMMAGPIE. It enables CPU cooling devices for this
target. Add the CPU to LMH-DCVSh hardware mapping.

Change-Id: I4c14c995345bb1315594a7a919cb90febb1a131e
Signed-off-by: default avatarManaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
parent e2e5fb8a

arch/arm64/boot/dts/qcom/atoll-thermal.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -13,6 +13,28 @@ 


#include <dt-bindings/thermal/thermal.h>



&clock_cpucc {

	#address-cells = <1>;

	#size-cells = <1>;

	lmh_dcvs0: qcom,limits-dcvs@18358800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18323000 0x1000>;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18325800 0x1000>;

		#thermal-sensor-cells = <0>;

	};

};



&soc {

	qmi-tmd-devices {

		compatible = "qcom,qmi-cooling-devices";

arch/arm64/boot/dts/qcom/atoll.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;
@@ -90,6 +91,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_100: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;
@@ -123,6 +125,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_200: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;
@@ -155,6 +158,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_300: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;
@@ -187,6 +191,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_400: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;
@@ -219,6 +224,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_500: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;
@@ -251,6 +257,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_600: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -292,6 +299,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_700: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;