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Commit 8323444b authored by venkatesh.pallipadi@intel.com's avatar venkatesh.pallipadi@intel.com Committed by Ingo Molnar
Browse files

x86: PAT Update validate_pat_support for intel CPUs 



Pentium III and Core Solo/Duo CPUs have an erratum
" Page with PAT set to WC while associated MTRR is UC may consolidate to UC "
which can result in WC setting in PAT to be ineffective. We will disable
PAT on such CPUs, so that we can continue to use MTRR WC setting.

Signed-off-by: default avatarVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 28df82eb

arch/x86/kernel/cpu/addon_cpuid_features.c

+15 −2
Original line number Original line Diff line number Diff line
@@ -56,9 +56,22 @@ void __cpuinit validate_pat_support(struct cpuinfo_x86 *c) 




	switch (c->x86_vendor) {

	switch (c->x86_vendor) {

	case X86_VENDOR_INTEL:

	case X86_VENDOR_INTEL:

		if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))

		/*

		 * There is a known erratum on Pentium III and Core Solo

		 * and Core Duo CPUs.

		 * " Page with PAT set to WC while associated MTRR is UC

		 *   may consolidate to UC "

		 * Because of this erratum, it is better to stick with

		 * setting WC in MTRR rather than using PAT on these CPUs.

		 *

		 * Enable PAT WC only on P4, Core 2 or later CPUs.

		 */

		if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15))

			return;

			return;

		break;



		pat_disable("PAT WC disabled due to known CPU erratum.");

		return;



	case X86_VENDOR_AMD:

	case X86_VENDOR_AMD:

	case X86_VENDOR_CENTAUR:

	case X86_VENDOR_CENTAUR:

	case X86_VENDOR_TRANSMETA:

	case X86_VENDOR_TRANSMETA: