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Commit 7ee9ae0e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add regulator and peripheral devices for SA8195"

parents 4b986ee8 2e07f2a2

arch/arm64/boot/dts/qcom/pm8195.dtsi

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/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/input/qcom,qpnp-power-on.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/spmi/spmi.h>

#include <dt-bindings/iio/qcom,spmi-vadc.h>



&spmi_bus {

	qcom,pm8195@0 {

		compatible = "qcom,spmi-pmic";

		reg = <0x0 SPMI_USID>;

		#address-cells = <2>;

		#size-cells = <0>;



		pm8195_1_tz: qcom,temp-alarm@2400 {

			compatible = "qcom,spmi-temp-alarm";

			reg = <0x2400 0x100>;

			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;

			#thermal-sensor-cells = <0>;

			qcom,temperature-threshold-set = <1>;

		};



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800 0x100>;

			interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,

				     <0x0 0x8 0x1 IRQ_TYPE_NONE>;

			interrupt-names = "kpdpwr", "resin";

			qcom,pon-dbc-delay = <15625>;

			qcom,kpdpwr-sw-debounce;

			qcom,system-reset;

			qcom,store-hard-reset-reason;



			qcom,pon_1 {

				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;

				qcom,pull-up = <1>;

				linux,code = <KEY_POWER>;

			};



			qcom,pon_2 {

				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;

				qcom,pull-up;

				linux,code = <KEY_VOLUMEDOWN>;

			};

		};



		pm8195_1_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00 0x200>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_1_div_clk1",

						"pm8195_1_div_clk2";

			clocks = <&clock_rpmh RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_1_rtc: qcom,pm8195_1_rtc {

			compatible = "qcom,qpnp-rtc";

			#address-cells = <1>;

			#size-cells = <1>;

			qcom,qpnp-rtc-write = <0>;

			qcom,qpnp-rtc-alarm-pwrup = <0>;



			qcom,pm8195_1_rtc_rw@6000 {

				reg = <0x6000 0x100>;

			};

			qcom,pm8195_1_rtc_alarm@6100 {

				reg = <0x6100 0x100>;

				interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;

			};

		};



		pm8195_1_gpios: pinctrl@c000 {

			compatible = "qcom,spmi-gpio";

			reg = <0xc000 0xa00>;

			interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,

					<0x0 0xc1 0 IRQ_TYPE_NONE>,

					<0x0 0xc2 0 IRQ_TYPE_NONE>,

					<0x0 0xc3 0 IRQ_TYPE_NONE>,

					<0x0 0xc4 0 IRQ_TYPE_NONE>,

					<0x0 0xc5 0 IRQ_TYPE_NONE>,

					<0x0 0xc6 0 IRQ_TYPE_NONE>,

					<0x0 0xc7 0 IRQ_TYPE_NONE>,

					<0x0 0xc8 0 IRQ_TYPE_NONE>,

					<0x0 0xc9 0 IRQ_TYPE_NONE>;

			interrupt-names = "pm8195_1_gpio1", "pm8195_1_gpio2",

					  "pm8195_1_gpio3", "pm8195_1_gpio4",

					  "pm8195_1_gpio5", "pm8195_1_gpio6",

					  "pm8195_1_gpio7", "pm8195_1_gpio8",

					  "pm8195_1_gpio9", "pm8195_1_gpio10";

			gpio-controller;

			#gpio-cells = <2>;

		};



		pm8195_1_sdam_2: sdam@b100 {

			compatible = "qcom,spmi-sdam";

			reg = <0xb100 0x100>;

		};



	};



	qcom,pm8195@1 {

		compatible ="qcom,spmi-pmic";

		reg = <0x1 SPMI_USID>;

		#address-cells = <2>;

		#size-cells = <0>;

	};



	/* below definitions are for the second instance of pm8195 */

	qcom,pm8195@4 {

		compatible = "qcom,spmi-pmic";

		reg = <0x4 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800 0x100>;

		};



		pm8195_2_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00 0x200>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_2_div_clk1",

						"pm8195_2_div_clk2";

			clocks = <&clock_rpmh RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_2_gpios: pinctrl@c000 {

			compatible = "qcom,spmi-gpio";

			reg = <0xc000 0xa00>;

			interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>,

					<0x4 0xc1 0 IRQ_TYPE_NONE>,

					<0x4 0xc2 0 IRQ_TYPE_NONE>,

					<0x4 0xc3 0 IRQ_TYPE_NONE>,

					<0x4 0xc4 0 IRQ_TYPE_NONE>,

					<0x4 0xc5 0 IRQ_TYPE_NONE>,

					<0x4 0xc6 0 IRQ_TYPE_NONE>,

					<0x4 0xc7 0 IRQ_TYPE_NONE>,

					<0x4 0xc8 0 IRQ_TYPE_NONE>,

					<0x4 0xc9 0 IRQ_TYPE_NONE>;

			interrupt-names = "pm8195_2_gpio1", "pm8195_2_gpio2",

					"pm8195_2_gpio3", "pm8195_2_gpio4",

					"pm8195_2_gpio5", "pm8195_2_gpio6",

					"pm8195_2_gpio7", "pm8195_2_gpio8",

					"pm8195_2_gpio9", "pm8195_2_gpio10";

			gpio-controller;

			#gpio-cells = <2>;

		};

	};



	qcom,pm8195@5 {

		compatible ="qcom,spmi-pmic";

		reg = <0x5 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;

	};



	/* below definitions are for the third instance of pm8195 */

	qcom,pm8195@8 {

		compatible = "qcom,spmi-pmic";

		reg = <0x8 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800 0x100>;

		};



		pm8195_3_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00 0x200>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_3_div_clk1",

						"pm8195_3_div_clk2";

			clocks = <&clock_rpmh RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_3_gpios: pinctrl@c000 {

			compatible = "qcom,spmi-gpio";

			reg = <0xc000 0xa00>;

			interrupts = <0x8 0xc0 0 IRQ_TYPE_NONE>,

					<0x8 0xc1 0 IRQ_TYPE_NONE>,

					<0x8 0xc2 0 IRQ_TYPE_NONE>,

					<0x8 0xc3 0 IRQ_TYPE_NONE>,

					<0x8 0xc4 0 IRQ_TYPE_NONE>,

					<0x8 0xc5 0 IRQ_TYPE_NONE>,

					<0x8 0xc6 0 IRQ_TYPE_NONE>,

					<0x8 0xc7 0 IRQ_TYPE_NONE>,

					<0x8 0xc8 0 IRQ_TYPE_NONE>,

					<0x8 0xc9 0 IRQ_TYPE_NONE>;

			interrupt-names = "pm8195_3_gpio1", "pm8195_3_gpio2",

					"pm8195_3_gpio3", "pm8195_3_gpio4",

					"pm8195_3_gpio5", "pm8195_3_gpio6",

					"pm8195_3_gpio7", "pm8195_3_gpio8",

					"pm8195_3_gpio9", "pm8195_3_gpio10";

			gpio-controller;

			#gpio-cells = <2>;

		};

	};



	qcom,pm8195@9 {

		compatible ="qcom,spmi-pmic";

		reg = <0x9 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

};



/* PMIC GPIO pin control configurations */

&pm8195_1_gpios {

	storage_sd_detect {

		storage_cd_default: storage_cd_default {

			pins = "gpio4";

			function = "normal";

			input-enable;

			bias-pull-up;

			power-source = <0>;

		};

	};



	key_vol_up {

		key_vol_up_default: key_vol_up_default {

			pins = "gpio6";

			function = "normal";

			input-enable;

			bias-pull-up;

			power-source = <1>;

		};

	};

};

arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi

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/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/* Remove regulator nodes specific to sdmshrike */

&soc {

	/* Stub regulators */

	/delete-node/ regulator-pm8150_1-s4;



	/* Logical rails */

	/delete-node/ rpmh-regulator-cxlvl;

	/delete-node/ rpmh-regulator-mxlvl;

	/delete-node/ rpmh-regulator-gfxlvl;

	/delete-node/ rpmh-regulator-lmxlvl;

	/delete-node/ rpmh-regulator-lcxlvl;

	/delete-node/ rpmh-regulator-mmcxlvl;

	/delete-node/ rpmh-regulator-msslvl;

	/delete-node/ rpmh-regulator-ebilvl;



	/* PM8150_1 regulators */

	/delete-node/ rpmh-regulator-smpa5;

	/delete-node/ rpmh-regulator-ldoa3;

	/delete-node/ rpmh-regulator-ldoa5;

	/delete-node/ rpmh-regulator-ldoa6;

	/delete-node/ rpmh-regulator-ldoa7;

	/delete-node/ rpmh-regulator-ldoa9;

	/delete-node/ rpmh-regulator-ldoa11;

	/delete-node/ rpmh-regulator-ldoa12;

	/delete-node/ rpmh-regulator-ldoa13;

	/delete-node/ rpmh-regulator-ldoa15;

	/delete-node/ rpmh-regulator-ldoa16;

	/delete-node/ rpmh-regulator-ldoa18;

	/delete-node/ rpmh-regulator-smpe4;

	/delete-node/ rpmh-regulator-smpe5;

	/delete-node/ rpmh-regulator-ldoe1;

	/delete-node/ rpmh-regulator-ldoe2;

	/delete-node/ rpmh-regulator-ldoe5;

	/delete-node/ rpmh-regulator-ldoe7;

	/delete-node/ rpmh-regulator-ldoe10;

	/delete-node/ rpmh-regulator-ldoe13;

	/delete-node/ rpmh-regulator-ldoe14;

	/delete-node/ rpmh-regulator-ldoe15;

	/delete-node/ rpmh-regulator-ldoe16;

	/delete-node/ rpmh-regulator-ldoe17;

	/delete-node/ rpmh-regulator-smpc6;

	/delete-node/ rpmh-regulator-smpc7;

	/delete-node/ rpmh-regulator-smpc8;

	/delete-node/ rpmh-regulator-ldoc1;

	/delete-node/ rpmh-regulator-ldoc2;

	/delete-node/ rpmh-regulator-ldoc3;

	/delete-node/ rpmh-regulator-ldoc4;

	/delete-node/ rpmh-regulator-ldoc6;

	/delete-node/ rpmh-regulator-ldoc7;

	/delete-node/ rpmh-regulator-ldoc8;

	/delete-node/ rpmh-regulator-ldoc9;

	/delete-node/ rpmh-regulator-ldoc10;

	/delete-node/ rpmh-regulator-ldoc11;

	/delete-node/ rpmh-regulator-bobc1;



	/* refgen-regulator@88e7000 */

	/delete-node/ refgen;

};



&usb2_phy0 {

	/delete-property/ vdd-supply;

	/delete-property/ vdda18-supply;

	/delete-property/ vdda33-supply;

};



&mdss_dsi0 {

	vdda-1p2-supply = <&pm8195_1_l9>;

};



&mdss_dsi1 {

	vdda-1p2-supply = <&pm8195_1_l9>;

};



&mdss_dsi_phy0 {

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&mdss_dsi_phy1 {

	vdda-0p9-supply = <&pm8195_3_l5>;

};



&clock_cpucc {

	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		isens_vref_0p8-supply = <&pm8195_3_l5>;

		isens-vref-0p8-settings = <880000 880000 20000>;

		isens_vref_1p8-supply = <&pm8195_1_l12>;

		isens-vref-1p8-settings = <1800000 1800000 20000>;

	};

};





&soc {

	qcom,lpass@17300000 {

		vdd_cx-supply = <&VDD_CX_LEVEL>;

	};

	clock_camcc: qcom,camcc@ad00000 {

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

	};

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_MMCX_LEVEL>;

	vdd_parent-supply = <&VDD_MMCX_LEVEL>;

};



#include "sa8195p-regulator.dtsi"

#include "pm8195.dtsi"

arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi

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 */



#include <dt-bindings/gpio/gpio.h>

#include "sa8195-pmic.dtsi"



&qupv3_se0_spi {

	status = "ok";

arch/arm64/boot/dts/qcom/sa8195p-regulator.dtsi

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