Loading Documentation/devicetree/bindings/regulator/gdsc-regulator.txt +5 −4 Original line number Diff line number Diff line Loading @@ -50,10 +50,11 @@ Optional properties: to enable. - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while enabling the GX GDSC. - qcom,vote-parent-supply-voltage: If present, need to vote for a minimum operational voltage (LOW_SVS) on the GDSC parent regulator prior to configuring it. The vote is removed once the GDSC FSM has latched on to the new state. - vdd_parent-supply: phandle to the regulator that this GDSC gates. If present, need to vote for a minimum operational voltage (LOW_SVS) on the GDSC parent regulator prior to configuring it. The vote is removed once the GDSC FSM has latched on to the new state. - resets: reset specifier pair consisting of phandle for the reset controller and reset lines used by this controller. These can be supplied only if we support qcom,skip-logic-collapse. Loading arch/arm64/boot/dts/qcom/sdmshrike.dtsi +13 −13 Original line number Diff line number Diff line Loading @@ -1264,7 +1264,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1272,7 +1272,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1280,7 +1280,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1288,7 +1288,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1296,7 +1296,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1304,7 +1304,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1312,7 +1312,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1320,7 +1320,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1328,7 +1328,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1338,7 +1338,7 @@ &gpu_gx_gdsc { parent-supply = <&pm855_1_s10_level>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&pm855_1_s10_level>; status = "ok"; }; Loading @@ -1346,7 +1346,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1354,7 +1354,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1362,7 +1362,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading arch/arm64/boot/dts/qcom/sm8150.dtsi +11 −11 Original line number Diff line number Diff line Loading @@ -3245,7 +3245,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3253,7 +3253,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3261,7 +3261,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3269,7 +3269,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3277,7 +3277,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3285,7 +3285,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3293,7 +3293,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3303,7 +3303,7 @@ &gpu_gx_gdsc { parent-supply = <&pm855l_s2_level>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&pm855l_s2_level>; status = "ok"; }; Loading @@ -3311,7 +3311,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3319,7 +3319,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3327,7 +3327,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading drivers/clk/qcom/gdsc-regulator.c +26 −19 Original line number Diff line number Diff line /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -60,6 +60,7 @@ struct gdsc { struct regmap *hw_ctrl; struct regmap *sw_reset; struct clk **clocks; struct regulator *parent_regulator; struct reset_control **reset_clocks; bool toggle_mem; bool toggle_periph; Loading @@ -71,7 +72,6 @@ struct gdsc { bool is_gdsc_enabled; bool allow_clear; bool reset_aon; bool vote_supply_voltage; int clock_count; int reset_count; int root_clk_idx; Loading Loading @@ -170,8 +170,8 @@ static int gdsc_enable(struct regulator_dev *rdev) mutex_lock(&gdsc_seq_lock); if (sc->vote_supply_voltage) { ret = regulator_set_voltage(sc->rdev->supply, if (sc->parent_regulator) { ret = regulator_set_voltage(sc->parent_regulator, RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX); if (ret) { mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -316,8 +316,8 @@ static int gdsc_enable(struct regulator_dev *rdev) sc->is_gdsc_enabled = true; end: if (sc->vote_supply_voltage) regulator_set_voltage(sc->rdev->supply, 0, INT_MAX); if (sc->parent_regulator) regulator_set_voltage(sc->parent_regulator, 0, INT_MAX); mutex_unlock(&gdsc_seq_lock); Loading @@ -332,8 +332,8 @@ static int gdsc_disable(struct regulator_dev *rdev) mutex_lock(&gdsc_seq_lock); if (sc->vote_supply_voltage) { ret = regulator_set_voltage(sc->rdev->supply, if (sc->parent_regulator) { ret = regulator_set_voltage(sc->parent_regulator, RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX); if (ret) { mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -398,8 +398,8 @@ static int gdsc_disable(struct regulator_dev *rdev) if ((sc->is_gdsc_enabled && sc->root_en) || sc->force_root_en) clk_disable_unprepare(sc->clocks[sc->root_clk_idx]); if (sc->vote_supply_voltage) regulator_set_voltage(sc->rdev->supply, 0, INT_MAX); if (sc->parent_regulator) regulator_set_voltage(sc->parent_regulator, 0, INT_MAX); sc->is_gdsc_enabled = false; Loading Loading @@ -431,8 +431,8 @@ static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) mutex_lock(&gdsc_seq_lock); if (sc->vote_supply_voltage) { ret = regulator_set_voltage(sc->rdev->supply, if (sc->parent_regulator) { ret = regulator_set_voltage(sc->parent_regulator, RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX); if (ret) { mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -483,8 +483,8 @@ static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) break; } if (sc->vote_supply_voltage) regulator_set_voltage(sc->rdev->supply, 0, INT_MAX); if (sc->parent_regulator) regulator_set_voltage(sc->parent_regulator, 0, INT_MAX); mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -602,8 +602,18 @@ static int gdsc_probe(struct platform_device *pdev) sc->force_root_en = of_property_read_bool(pdev->dev.of_node, "qcom,force-enable-root-clk"); sc->vote_supply_voltage = of_property_read_bool(pdev->dev.of_node, "qcom,vote-parent-supply-voltage"); if (of_find_property(pdev->dev.of_node, "vdd_parent-supply", NULL)) { sc->parent_regulator = devm_regulator_get(&pdev->dev, "vdd_parent"); if (IS_ERR(sc->parent_regulator)) { ret = PTR_ERR(sc->parent_regulator); if (ret != -EPROBE_DEFER) dev_err(&pdev->dev, "Unable to get vdd_parent regulator, err: %d\n", ret); return ret; } } for (i = 0; i < sc->clock_count; i++) { const char *clock_name; Loading Loading @@ -749,9 +759,6 @@ static int gdsc_probe(struct platform_device *pdev) return PTR_ERR(sc->rdev); } if (!sc->rdev->supply) sc->vote_supply_voltage = false; return 0; } Loading Loading
Documentation/devicetree/bindings/regulator/gdsc-regulator.txt +5 −4 Original line number Diff line number Diff line Loading @@ -50,10 +50,11 @@ Optional properties: to enable. - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while enabling the GX GDSC. - qcom,vote-parent-supply-voltage: If present, need to vote for a minimum operational voltage (LOW_SVS) on the GDSC parent regulator prior to configuring it. The vote is removed once the GDSC FSM has latched on to the new state. - vdd_parent-supply: phandle to the regulator that this GDSC gates. If present, need to vote for a minimum operational voltage (LOW_SVS) on the GDSC parent regulator prior to configuring it. The vote is removed once the GDSC FSM has latched on to the new state. - resets: reset specifier pair consisting of phandle for the reset controller and reset lines used by this controller. These can be supplied only if we support qcom,skip-logic-collapse. Loading
arch/arm64/boot/dts/qcom/sdmshrike.dtsi +13 −13 Original line number Diff line number Diff line Loading @@ -1264,7 +1264,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1272,7 +1272,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1280,7 +1280,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1288,7 +1288,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1296,7 +1296,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1304,7 +1304,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1312,7 +1312,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1320,7 +1320,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1328,7 +1328,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1338,7 +1338,7 @@ &gpu_gx_gdsc { parent-supply = <&pm855_1_s10_level>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&pm855_1_s10_level>; status = "ok"; }; Loading @@ -1346,7 +1346,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1354,7 +1354,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -1362,7 +1362,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading
arch/arm64/boot/dts/qcom/sm8150.dtsi +11 −11 Original line number Diff line number Diff line Loading @@ -3245,7 +3245,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3253,7 +3253,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3261,7 +3261,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3269,7 +3269,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3277,7 +3277,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3285,7 +3285,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3293,7 +3293,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3303,7 +3303,7 @@ &gpu_gx_gdsc { parent-supply = <&pm855l_s2_level>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&pm855l_s2_level>; status = "ok"; }; Loading @@ -3311,7 +3311,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3319,7 +3319,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading @@ -3327,7 +3327,7 @@ clock-names = "ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; parent-supply = <&VDD_MMCX_LEVEL>; qcom,vote-parent-supply-voltage; vdd_parent-supply = <&VDD_MMCX_LEVEL>; status = "ok"; }; Loading
drivers/clk/qcom/gdsc-regulator.c +26 −19 Original line number Diff line number Diff line /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -60,6 +60,7 @@ struct gdsc { struct regmap *hw_ctrl; struct regmap *sw_reset; struct clk **clocks; struct regulator *parent_regulator; struct reset_control **reset_clocks; bool toggle_mem; bool toggle_periph; Loading @@ -71,7 +72,6 @@ struct gdsc { bool is_gdsc_enabled; bool allow_clear; bool reset_aon; bool vote_supply_voltage; int clock_count; int reset_count; int root_clk_idx; Loading Loading @@ -170,8 +170,8 @@ static int gdsc_enable(struct regulator_dev *rdev) mutex_lock(&gdsc_seq_lock); if (sc->vote_supply_voltage) { ret = regulator_set_voltage(sc->rdev->supply, if (sc->parent_regulator) { ret = regulator_set_voltage(sc->parent_regulator, RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX); if (ret) { mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -316,8 +316,8 @@ static int gdsc_enable(struct regulator_dev *rdev) sc->is_gdsc_enabled = true; end: if (sc->vote_supply_voltage) regulator_set_voltage(sc->rdev->supply, 0, INT_MAX); if (sc->parent_regulator) regulator_set_voltage(sc->parent_regulator, 0, INT_MAX); mutex_unlock(&gdsc_seq_lock); Loading @@ -332,8 +332,8 @@ static int gdsc_disable(struct regulator_dev *rdev) mutex_lock(&gdsc_seq_lock); if (sc->vote_supply_voltage) { ret = regulator_set_voltage(sc->rdev->supply, if (sc->parent_regulator) { ret = regulator_set_voltage(sc->parent_regulator, RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX); if (ret) { mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -398,8 +398,8 @@ static int gdsc_disable(struct regulator_dev *rdev) if ((sc->is_gdsc_enabled && sc->root_en) || sc->force_root_en) clk_disable_unprepare(sc->clocks[sc->root_clk_idx]); if (sc->vote_supply_voltage) regulator_set_voltage(sc->rdev->supply, 0, INT_MAX); if (sc->parent_regulator) regulator_set_voltage(sc->parent_regulator, 0, INT_MAX); sc->is_gdsc_enabled = false; Loading Loading @@ -431,8 +431,8 @@ static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) mutex_lock(&gdsc_seq_lock); if (sc->vote_supply_voltage) { ret = regulator_set_voltage(sc->rdev->supply, if (sc->parent_regulator) { ret = regulator_set_voltage(sc->parent_regulator, RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX); if (ret) { mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -483,8 +483,8 @@ static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) break; } if (sc->vote_supply_voltage) regulator_set_voltage(sc->rdev->supply, 0, INT_MAX); if (sc->parent_regulator) regulator_set_voltage(sc->parent_regulator, 0, INT_MAX); mutex_unlock(&gdsc_seq_lock); Loading Loading @@ -602,8 +602,18 @@ static int gdsc_probe(struct platform_device *pdev) sc->force_root_en = of_property_read_bool(pdev->dev.of_node, "qcom,force-enable-root-clk"); sc->vote_supply_voltage = of_property_read_bool(pdev->dev.of_node, "qcom,vote-parent-supply-voltage"); if (of_find_property(pdev->dev.of_node, "vdd_parent-supply", NULL)) { sc->parent_regulator = devm_regulator_get(&pdev->dev, "vdd_parent"); if (IS_ERR(sc->parent_regulator)) { ret = PTR_ERR(sc->parent_regulator); if (ret != -EPROBE_DEFER) dev_err(&pdev->dev, "Unable to get vdd_parent regulator, err: %d\n", ret); return ret; } } for (i = 0; i < sc->clock_count; i++) { const char *clock_name; Loading Loading @@ -749,9 +759,6 @@ static int gdsc_probe(struct platform_device *pdev) return PTR_ERR(sc->rdev); } if (!sc->rdev->supply) sc->vote_supply_voltage = false; return 0; } Loading