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Commit 78a6ba73 authored by jiad's avatar jiad Committed by Gerrit - the friendly Code Review server
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cnss2: disable PCIe L1SS after restoring config space 



L1SS is a PCIe extended capability and its state is not saved when
pci_save_state() is invoked. Thus explicitly disable L1SS after
PCIe state is restored.

Change-Id: I7e4d91e7ec48121be13cb148e3aeb5804fb0119e
Signed-off-by: default avatarJia Ding <jiad@codeaurora.org>
parent 681f798f

drivers/net/wireless/cnss2/pci.c

+59 −60
Original line number Diff line number Diff line
@@ -162,6 +162,61 @@ static u32 cnss_pci_reg_read(struct cnss_pci_data *pci_priv, u32 offset) 
			     (offset & WINDOW_RANGE_MASK));

}



static void cnss_pci_disable_l1(struct cnss_pci_data *pci_priv)

{

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;

	struct pci_dev *pdev = pci_priv->pci_dev;

	bool disable_l1;

	u32 lnkctl_offset;

	u32 val;



	disable_l1 = of_property_read_bool(plat_priv->dev_node,

					   "pcie-disable-l1");

	cnss_pr_dbg("disable_l1 %d\n", disable_l1);



	if (!disable_l1)

		return;



	lnkctl_offset = pdev->pcie_cap + PCI_EXP_LNKCTL;

	pci_read_config_dword(pdev, lnkctl_offset, &val);

	cnss_pr_dbg("lnkctl 0x%x\n", val);



	val &= ~PCI_EXP_LNKCTL_ASPM_L1;

	pci_write_config_dword(pdev, lnkctl_offset, val);

}



static void cnss_pci_disable_l1ss(struct cnss_pci_data *pci_priv)

{

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;

	struct pci_dev *pdev = pci_priv->pci_dev;

	bool disable_l1ss;

	u32 l1ss_cap_id_offset;

	u32 l1ss_ctl1_offset;

	u32 val;



	disable_l1ss = of_property_read_bool(plat_priv->dev_node,

					     "pcie-disable-l1ss");

	cnss_pr_dbg("disable_l1ss %d\n", disable_l1ss);



	if (!disable_l1ss)

		return;



	l1ss_cap_id_offset = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);

	if (!l1ss_cap_id_offset) {

		cnss_pr_dbg("could not find L1ss capability register\n");

		return;

	}



	l1ss_ctl1_offset = l1ss_cap_id_offset + PCI_L1SS_CTL1;



	pci_read_config_dword(pdev, l1ss_ctl1_offset, &val);

	cnss_pr_dbg("l1ss_ctl1 0x%x\n", val);



	val &= ~(PCI_L1SS_CTL1_PCIPM_L1_1 | PCI_L1SS_CTL1_PCIPM_L1_2 |

		 PCI_L1SS_CTL1_ASPM_L1_1 | PCI_L1SS_CTL1_ASPM_L1_2);

	pci_write_config_dword(pdev, l1ss_ctl1_offset, val);

}



static int cnss_set_pci_config_space(struct cnss_pci_data *pci_priv, bool save)

{

	struct pci_dev *pci_dev = pci_priv->pci_dev;
@@ -190,6 +245,8 @@ static int cnss_set_pci_config_space(struct cnss_pci_data *pci_priv, bool save) 
						      &pci_priv->saved_state);

			pci_restore_state(pci_dev);

		}



		cnss_pci_disable_l1ss(pci_priv);

	}



	return 0;
@@ -2825,63 +2882,6 @@ static int cnss_pci_get_smmu_cfg(struct cnss_plat_data *plat_priv) 
	return ret;

}



static void cnss_pci_disable_l1(struct cnss_pci_data *pci_priv)

{

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;

	struct pci_dev *pdev = pci_priv->pci_dev;

	bool disable_l1 = false;

	u32 lnkctl_offset;

	u32 val;



	if (of_property_read_bool(plat_priv->dev_node, "pcie-disable-l1"))

		disable_l1 = true;



	cnss_pr_dbg("disable_l1 %d\n", disable_l1);



	if (!disable_l1)

		return;



	lnkctl_offset = pdev->pcie_cap + PCI_EXP_LNKCTL;

	pci_read_config_dword(pdev, lnkctl_offset, &val);

	cnss_pr_dbg("lnkctl 0x%x\n", val);



	val &= ~PCI_EXP_LNKCTL_ASPM_L1;

	pci_write_config_dword(pdev, lnkctl_offset, val);

}



static void cnss_pci_disable_l1ss(struct cnss_pci_data *pci_priv)

{

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;

	struct pci_dev *pdev = pci_priv->pci_dev;

	bool disable_l1ss = false;

	u32 l1ss_cap_id_offset;

	u32 l1ss_ctl1_offset;

	u32 val;



	if (of_property_read_bool(plat_priv->dev_node, "pcie-disable-l1ss"))

		disable_l1ss = true;



	cnss_pr_dbg("disable_l1ss %d\n", disable_l1ss);



	if (!disable_l1ss)

		return;



	l1ss_cap_id_offset = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);

	if (!l1ss_cap_id_offset) {

		cnss_pr_dbg("could not find L1ss capability register\n");

		return;

	}



	l1ss_ctl1_offset = l1ss_cap_id_offset + PCI_L1SS_CTL1;



	pci_read_config_dword(pdev, l1ss_ctl1_offset, &val);

	cnss_pr_dbg("l1ss_ctl1 0x%x\n", val);



	val &= ~(PCI_L1SS_CTL1_PCIPM_L1_1 | PCI_L1SS_CTL1_PCIPM_L1_2 |

		 PCI_L1SS_CTL1_ASPM_L1_1 | PCI_L1SS_CTL1_ASPM_L1_2);

	pci_write_config_dword(pdev, l1ss_ctl1_offset, val);

}



static int cnss_pci_probe(struct pci_dev *pci_dev,

			  const struct pci_device_id *id)

{
@@ -2948,12 +2948,11 @@ static int cnss_pci_probe(struct pci_dev *pci_dev, 
	if (ret)

		goto dereg_pci_event;



	cnss_pci_disable_l1(pci_priv);



	pci_save_state(pci_dev);

	pci_priv->default_state = pci_store_saved_state(pci_dev);



	cnss_pci_disable_l1(pci_priv);

	cnss_pci_disable_l1ss(pci_priv);



	switch (pci_dev->device) {

	case QCA6174_DEVICE_ID:

		pci_read_config_word(pci_dev, QCA6174_REV_ID_OFFSET,