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Commit 743155ea authored by Chris Lew's avatar Chris Lew
Browse files

ARM: dts: msm: Change QMP interrupt register for SM8150 



Current IPC interrupts to NPU are not configured correctly. Switch to
a spare control register and update the mask values needed to trigger
and interrupt to NPU.

Change-Id: Ia1ca29e874f8dfb85ec7d73ace7be0566b55f5cf
Signed-off-by: default avatarChris Lew <clew@codeaurora.org>
parent 1eeff766

arch/arm64/boot/dts/qcom/sm8150.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -2802,9 +2802,9 @@ 


	qmp_npu0: qcom,qmp-npu-low@9818000 {

		compatible = "qcom,qmp-mbox";

		reg = <0x9818000 0x8000>, <0x17c00010 0x4>;

		reg = <0x9818000 0x8000>, <0x9901008 0x4>;

		reg-names = "msgram", "irq-reg-base";

		qcom,irq-mask = <0x20>;

		qcom,irq-mask = <0x12>;

		interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;



		label = "npu_qmp_low";
@@ -2813,11 +2813,11 @@ 
		#mbox-cells = <1>;

	};



	qmp_npu1: qcom,qmp-npu-high@981a000 {

	qmp_npu1: qcom,qmp-npu-high@9818000 {

		compatible = "qcom,qmp-mbox";

		reg = <0x9818000 0x8000>, <0x17c00010 0x4>;

		reg = <0x9818000 0x8000>, <0x9901008 0x4>;

		reg-names = "msgram", "irq-reg-base";

		qcom,irq-mask = <0x40>;

		qcom,irq-mask = <0x14>;

		interrupts = <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>;



		label = "npu_qmp_high";