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Commit 6fcfb5a1 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes... 

Merge changes Ia305dfe1,Idc1aa697,Ia7dfa5f0,Ifb5ab5cb,I9c0dd060,Iee86ef80,I47f8fa55,I72558d4c,Id6ee5368,I0cd21b72,I5a1a9a6c,I017ac0c0,Id1c0f1d9,I7247cec9,I8327624e,I46aa16b6,Ic5b95ea0,I57f921ce,I9f8e5cf7 into msm-4.14

* changes:
  msm: kgsl: Use usleep_delay instead of cond_resched.
  msm: kgsl: GMU OOB set and clear calls shall be paired
  msm: kgsl: Make snapshot priority configurable
  msm: kgsl: Dump debugbus data in gmu snapshot
  msm: kgsl: Take gpu snapshot if fenced write fails
  msm: kgsl: Update thermal level via OPP notifier
  msm: kgsl: Extend GMU idle timeout
  msm: kgsl: Program SMMU aperture only if tz support
  msm: kgsl: Sync up time stamps with XO clock.
  msm: kgsl: Add a check for availability of RBBM timer clock
  msm: kgsl: Log clk set, enable and prepare failure
  msm: kgsl: Move global memory region to 0x100000000
  msm: kgsl: Create GPU device node based on gfx fuse
  msm: kgsl: Check the snapshot structure before dereferencing
  msm: kgsl: Fix attributes of read only files
  msm: kgsl: Update GMU FW version for A630 and A615
  msm: kgsl: Add a quirk to limit UCHE to GBIF read/write transactions
  msm: kgsl: Remove CP_ADDR_MODE_CNTL from powerup register list
  msm: kgsl: Enable inter-frame power collapse on A615
parents d3c896cf 4620c7ed

Documentation/devicetree/bindings/gpu/adreno.txt

+9 −0
Original line number Diff line number Diff line
@@ -124,6 +124,12 @@ Optional Properties: 
				mask   - mask for the relevant bits in the efuse register.

				shift  - number of bits to right shift to get the speed bin

				value.

- qcom,gpu-disable-fuse:	GPU disable fuse

				<offset mask shift>

				offset - offset of the efuse register from the base.

				mask   - mask for the relevant bits in the efuse register.

				shift  - number of bits to right shift to get the disable_gpu

				fuse bit value.

- qcom,highest-bank-bit:

				Specify the bit of the highest DDR bank. This

				is programmed into protected registers and also
@@ -191,6 +197,9 @@ GPU Quirks: 
- qcom,gpu-quirk-hfi-use-reg:

				Use registers to replace DCVS HFI message to avoid GMU failure

				to access system memory during IFPC

- qcom,gpu-quirk-limit-uche-gbif-rw:

				Limit number of read and write transactions from UCHE block to

				GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.



KGSL Memory Pools:

- qcom,gpu-mempools:		Container for sets of GPU mempools.Multiple sets

drivers/gpu/msm/a6xx_reg.h

+3 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -941,6 +941,8 @@ 
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H	0x1F84D

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L	0x1F84E

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H	0x1F84F

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L	0x1F888

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H	0x1F889

#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL	0x1F8C0

#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST	0x1F8C1

#define A6XX_GMU_PWR_COL_SPTPRAC_HYST		0x1F8C2

drivers/gpu/msm/adreno-gpulist.h

+6 −6
Original line number Diff line number Diff line 
/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -335,8 +335,8 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x0,

		.gpmu_minor = 0x005,

		.gpmu_major = 0x1,

		.gpmu_minor = 0x003,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

	},
@@ -357,7 +357,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x001,

		.gpmu_minor = 0x003,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

	},
@@ -368,7 +368,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.minor = 5,

		.patchid = ANY_ID,

		.features = ADRENO_64BIT | ADRENO_RPMH |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION,

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a615_zap",

		.gpudev = &adreno_a6xx_gpudev,
@@ -377,6 +377,6 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x001,

		.gpmu_minor = 0x003,

	},

};

drivers/gpu/msm/adreno.c

+36 −7
Original line number Diff line number Diff line
@@ -946,6 +946,8 @@ static struct { 
			"qcom,gpu-quirk-lmloadkill-disable" },

	{ ADRENO_QUIRK_HFI_USE_REG, "qcom,gpu-quirk-hfi-use-reg" },

	{ ADRENO_QUIRK_SECVID_SET_ONCE, "qcom,gpu-quirk-secvid-set-once" },

	{ ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW,

			"qcom,gpu-quirk-limit-uche-gbif-rw" },

};



static int adreno_of_get_power(struct adreno_device *adreno_dev,
@@ -1084,6 +1086,33 @@ static void adreno_cx_dbgc_probe(struct kgsl_device *device) 
		KGSL_DRV_WARN(device, "cx_dbgc ioremap failed\n");

}



static bool adreno_is_gpu_disabled(struct adreno_device *adreno_dev)

{

	unsigned int row0;

	unsigned int pte_row0_msb[3];

	int ret;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (of_property_read_u32_array(device->pdev->dev.of_node,

		"qcom,gpu-disable-fuse", pte_row0_msb, 3))

		return false;

	/*

	 * Read the fuse value to disable GPU driver if fuse

	 * is blown. By default(fuse value is 0) GPU is enabled.

	 */

	if (adreno_efuse_map(adreno_dev))

		return false;



	ret = adreno_efuse_read_u32(adreno_dev, pte_row0_msb[0], &row0);

	adreno_efuse_unmap(adreno_dev);



	if (ret)

		return false;



	return (row0 >> pte_row0_msb[2]) &

			pte_row0_msb[1] ? true : false;

}



static int adreno_probe(struct platform_device *pdev)

{

	struct kgsl_device *device;
@@ -1100,6 +1129,11 @@ static int adreno_probe(struct platform_device *pdev) 
	device = KGSL_DEVICE(adreno_dev);

	device->pdev = pdev;



	if (adreno_is_gpu_disabled(adreno_dev)) {

		pr_err("adreno: GPU is disabled on this device\n");

		return -ENODEV;

	}



	/* Get the chip ID from the DT and set up target specific parameters */

	adreno_identify_gpu(adreno_dev);
@@ -1483,7 +1517,7 @@ static void _set_secvid(struct kgsl_device *device) 
		adreno_writereg64(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

			KGSL_IOMMU_SECURE_BASE);

			KGSL_IOMMU_SECURE_BASE(&device->mmu));

		adreno_writereg(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

			KGSL_IOMMU_SECURE_SIZE);
@@ -1814,11 +1848,6 @@ static int _adreno_start(struct adreno_device *adreno_dev) 


error_mmu_off:

	kgsl_mmu_stop(&device->mmu);

	if (gpudev->oob_clear &&

			ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) {

		gpudev->oob_clear(adreno_dev,

				OOB_BOOT_SLUMBER_CLEAR_MASK);

	}



error_pwr_off:

	/* set the state back to original state */
@@ -2072,7 +2101,7 @@ static int adreno_getproperty(struct kgsl_device *device, 
				 * anything to mmap().

				 */

				shadowprop.gpuaddr =

					(unsigned int) device->memstore.gpuaddr;

					(unsigned long)device->memstore.gpuaddr;

				shadowprop.size = device->memstore.size;

				/* GSL needs this to be set, even if it

				 * appears to be meaningless

drivers/gpu/msm/adreno.h

+7 −1
Original line number Diff line number Diff line
@@ -144,6 +144,12 @@ 
#define ADRENO_QUIRK_HFI_USE_REG BIT(6)

/* Only set protected SECVID registers once */

#define ADRENO_QUIRK_SECVID_SET_ONCE BIT(7)

/*

 * Limit number of read and write transactions from

 * UCHE block to GBIF to avoid possible deadlock

 * between GBIF, SMMU and MEMNOC.

 */

#define ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW BIT(8)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0
@@ -1949,7 +1955,7 @@ static inline int adreno_vbif_clear_pending_transactions( 
	return ret;

}



void adreno_gmu_fenced_write(struct adreno_device *adreno_dev,

int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,

	enum adreno_regs offset, unsigned int val,

	unsigned int fence_mask);

#endif /*__ADRENO_H */