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Commit 6f035408 authored by Skylar Chang's avatar Skylar Chang
Browse files

msm: ipa: enable GSI interrupt moderation 



Enable 0.5ms and 20 packets interrupt moderation in GSI
for WAN downlink pipe. To make sure latecy does not change
aggregation timer is reduced to 0.5ms from 1ms.

CRs-Fixed: 2202013
Change-Id: I567082f44d6842bb090133cca72a1db6d8921fc1
Acked-by: default avatarAdy Abraham <adya@qti.qualcomm.com>
Signed-off-by: default avatarSkylar Chang <chiaweic@codeaurora.org>
parent b2bdf7dc

drivers/platform/msm/gsi/gsi.c

+2 −0
Original line number Diff line number Diff line
@@ -2602,6 +2602,8 @@ int gsi_poll_channel(unsigned long chan_hdl, 
	spin_lock_irqsave(&ctx->evtr->ring.slock, flags);

	if (ctx->evtr->ring.rp == ctx->evtr->ring.rp_local) {

		/* update rp to see of we have anything new to process */

		gsi_writel(1 << ctx->evtr->id, gsi_ctx->base +

			GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(ee));

		rp = gsi_readl(gsi_ctx->base +

			GSI_EE_n_EV_CH_k_CNTXT_4_OFFS(ctx->evtr->id, ee));

		rp |= ctx->ring.rp & 0xFFFFFFFF00000000;

drivers/platform/msm/ipa/ipa_v3/ipa_dp.c

+12 −3
Original line number Diff line number Diff line
@@ -62,7 +62,8 @@ 
#define IPA_SIZE_DL_CSUM_META_TRAILER 8



#define IPA_GSI_MAX_CH_LOW_WEIGHT 15

#define IPA_GSI_EVT_RING_INT_MODT (32 * 1) /* 1ms under 32KHz clock */

#define IPA_GSI_EVT_RING_INT_MODT (16) /* 0.5ms under 32KHz clock */

#define IPA_GSI_EVT_RING_INT_MODC (20)



#define IPA_GSI_CH_20_WA_NUM_CH_TO_ALLOC 10

/* The below virtual channel cannot be used by any entity */
@@ -1758,6 +1759,7 @@ static void ipa3_replenish_rx_cache(struct ipa3_sys_context *sys) 
		gsi_xfer_elem_one.len = sys->rx_buff_sz;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOT;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOB;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_BEI;

		gsi_xfer_elem_one.type = GSI_XFER_ELEM_DATA;

		gsi_xfer_elem_one.xfer_user_data = rx_pkt;
@@ -1860,6 +1862,7 @@ static void ipa3_replenish_rx_cache_recycle(struct ipa3_sys_context *sys) 
		gsi_xfer_elem_one.len = sys->rx_buff_sz;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOT;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOB;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_BEI;

		gsi_xfer_elem_one.type = GSI_XFER_ELEM_DATA;

		gsi_xfer_elem_one.xfer_user_data = rx_pkt;
@@ -1925,6 +1928,7 @@ static void ipa3_fast_replenish_rx_cache(struct ipa3_sys_context *sys) 
		gsi_xfer_elem_one.len = sys->rx_buff_sz;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOT;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_EOB;

		gsi_xfer_elem_one.flags |= GSI_XFER_FLAG_BEI;

		gsi_xfer_elem_one.type = GSI_XFER_ELEM_DATA;

		gsi_xfer_elem_one.xfer_user_data = rx_pkt;
@@ -3567,8 +3571,13 @@ static int ipa_gsi_setup_channel(struct ipa_sys_connect_params *in, 
		ep->gsi_mem_info.evt_ring_base_vaddr =

			gsi_evt_ring_props.ring_base_vaddr;



		if (ep->napi_enabled) {

			gsi_evt_ring_props.int_modt = IPA_GSI_EVT_RING_INT_MODT;

			gsi_evt_ring_props.int_modc = IPA_GSI_EVT_RING_INT_MODC;

		} else {

			gsi_evt_ring_props.int_modt = IPA_GSI_EVT_RING_INT_MODT;

			gsi_evt_ring_props.int_modc = 1;

		}



		IPADBG("client=%d moderation threshold cycles=%u cnt=%u\n",

			ep->client,

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+5 −0
Original line number Diff line number Diff line
@@ -2228,6 +2228,7 @@ int ipa3_init_hw(void) 
{

	u32 ipa_version = 0;

	u32 val;

	struct ipahal_reg_counter_cfg cnt_cfg;



	/* Read IPA version and make sure we have access to the registers */

	ipa_version = ipahal_read_reg(IPA_VERSION);
@@ -2273,6 +2274,10 @@ int ipa3_init_hw(void) 


	ipa3_cfg_qsb();



	/* set granularity for 0.5 msec*/

	cnt_cfg.aggr_granularity = GRAN_VALUE_500_USEC;

	ipahal_write_reg_fields(IPA_COUNTER_CFG, &cnt_cfg);



	return 0;

}

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+28 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ static const char *ipareg_name_to_str[IPA_REG_MAX] = { 
	__stringify(IPA_SPARE_REG_2),

	__stringify(IPA_COMP_CFG),

	__stringify(IPA_STATE_AGGR_ACTIVE),

	__stringify(IPA_COUNTER_CFG),

	__stringify(IPA_ENDP_INIT_HDR_n),

	__stringify(IPA_ENDP_INIT_HDR_EXT_n),

	__stringify(IPA_ENDP_INIT_AGGR_n),
@@ -1449,6 +1450,30 @@ static void ipareg_parse_hps_queue_weights( 
		IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK);

}



static void ipareg_construct_counter_cfg(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	struct ipahal_reg_counter_cfg *counter_cfg =

		(struct ipahal_reg_counter_cfg *)fields;



	IPA_SETFIELD_IN_REG(*val, counter_cfg->aggr_granularity,

		IPA_COUNTER_CFG_AGGR_GRANULARITY_SHFT,

		IPA_COUNTER_CFG_AGGR_GRANULARITY_BMSK);

}



static void ipareg_parse_counter_cfg(

	enum ipahal_reg_name reg, void *fields, u32 val)

{

	struct ipahal_reg_counter_cfg *counter_cfg =

		(struct ipahal_reg_counter_cfg *)fields;



	memset(counter_cfg, 0, sizeof(*counter_cfg));



	counter_cfg->aggr_granularity = IPA_GETFIELD_FROM_REG(val,

		IPA_COUNTER_CFG_AGGR_GRANULARITY_SHFT,

		IPA_COUNTER_CFG_AGGR_GRANULARITY_BMSK);

}



/*

 * struct ipahal_reg_obj - Register H/W information for specific IPA version

 * @construct - CB to construct register value from abstracted structure
@@ -1741,6 +1766,9 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
	[IPA_HW_v3_5][IPA_HPS_FTCH_ARB_QUEUE_WEIGHT] = {

		ipareg_construct_hps_queue_weights,

		ipareg_parse_hps_queue_weights, 0x000005a4, 0},

	[IPA_HW_v3_5][IPA_COUNTER_CFG] = {

		ipareg_construct_counter_cfg, ipareg_parse_counter_cfg,

		0x000001F0, 0 },



	/* IPAv4.0 */

	[IPA_HW_v4_0][IPA_ENDP_INIT_CTRL_n] = {

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

+16 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ enum ipahal_reg_name { 
	IPA_SPARE_REG_2,

	IPA_COMP_CFG,

	IPA_STATE_AGGR_ACTIVE,

	IPA_COUNTER_CFG,

	IPA_ENDP_INIT_HDR_n,

	IPA_ENDP_INIT_HDR_EXT_n,

	IPA_ENDP_INIT_AGGR_n,
@@ -349,6 +350,21 @@ struct ipahal_reg_rx_hps_weights { 
	u32 hps_queue_weight_3;

};



/*

 * struct ipahal_reg_counter_cfg - granularity of counter registers

 * @aggr_granularity  -Defines the granularity of AGGR timers

 *	granularity [msec]=(x+1)/(32)

 */

struct ipahal_reg_counter_cfg {

	enum {

		GRAN_VALUE_125_USEC = 3,

		GRAN_VALUE_250_USEC = 7,

		GRAN_VALUE_500_USEC = 15,

		GRAN_VALUE_MSEC = 31,

	} aggr_granularity;

};





/*

 * struct ipahal_reg_valmask - holding values and masking for registers

 *	HAL application may require only value and mask of it for some