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Commit 6ef5fb2c authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
Browse files

sh: intc - add a clear register to struct intc_prio_reg 



We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.

Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent d6aee69c

arch/sh/kernel/cpu/irq/intc.c

+4 −4
Original line number Diff line number Diff line
@@ -59,14 +59,14 @@ static inline unsigned int set_prio_field(struct intc_desc *desc, 


static void disable_prio_16(struct intc_desc *desc, unsigned int data)

{

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;



	ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);

}



static void enable_prio_16(struct intc_desc *desc, unsigned int data)

{

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;

	unsigned int prio = _INTC_VALUE(data);



	ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
@@ -74,14 +74,14 @@ static void enable_prio_16(struct intc_desc *desc, unsigned int data) 


static void disable_prio_32(struct intc_desc *desc, unsigned int data)

{

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;



	ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);

}



static void enable_prio_32(struct intc_desc *desc, unsigned int data)

{

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;

	unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;

	unsigned int prio = _INTC_VALUE(data);



	ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);

arch/sh/kernel/cpu/sh3/setup-sh7705.c

+8 −8
Original line number Diff line number Diff line
@@ -73,14 +73,14 @@ static struct intc_prio priorities[] = { 
};



static struct intc_prio_reg prio_registers[] = {

	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },

	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },

	{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },

	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },

	{ 0xa4080000, 16, 4, /* IPRF */ { 0, 0, USB } },

	{ 0xa4080002, 16, 4, /* IPRG */ { TPU0, TPU1 } },

	{ 0xa4080004, 16, 4, /* IPRH */ { TPU2, TPU3 } },

	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },

	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },

	{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },

	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },

	{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },

	{ 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },

	{ 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },



};

arch/sh/kernel/cpu/sh3/setup-sh770x.c

+8 −8
Original line number Diff line number Diff line
@@ -89,22 +89,22 @@ static struct intc_prio priorities[] = { 
};



static struct intc_prio_reg prio_registers[] = {

	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },

	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },

#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \

    defined(CONFIG_CPU_SUBTYPE_SH7707) || \

    defined(CONFIG_CPU_SUBTYPE_SH7709)

	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },

	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },

	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },

	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },

	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },

	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },

#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \

    defined(CONFIG_CPU_SUBTYPE_SH7709)

	{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, } },

	{ 0xa400001a, 16, 4, /* IPRE */ { 0, SCIF0 } },

	{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },

	{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },

#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7707)

	{ 0xa400001c, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },

	{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },

#endif

};

arch/sh/kernel/cpu/sh3/setup-sh7710.c

+10 −10
Original line number Diff line number Diff line
@@ -86,18 +86,18 @@ static struct intc_prio priorities[] = { 
};



static struct intc_prio_reg prio_registers[] = {

	{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },

	{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },

	{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },

	{ 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },

	{ 0xa4080000, 16, 4, /* IPRF */ { 0, DMAC2 } },

	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },

	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },

	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },

	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },

	{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },

#ifdef CONFIG_CPU_SUBTYPE_SH7710

	{ 0xa4080000, 16, 4, /* IPRF */ { IPSEC } },

	{ 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },

#endif

	{ 0xa4080002, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },

	{ 0xa4080004, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },

	{ 0xa4080006, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },

	{ 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },

	{ 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },

	{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },

};



static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,

arch/sh/kernel/cpu/sh4/setup-sh7750.c

+7 −7
Original line number Diff line number Diff line
@@ -133,11 +133,11 @@ static struct intc_prio priorities[] = { 
};



static struct intc_prio_reg prio_registers[] = {

	{ 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },

	{ 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },

	{ 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },

	{ 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,

	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },

	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },

	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },

	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,

						 TMU4, TMU3,

						 PCIC1, PCIC0_PCISERR } },

};