Commit 6c2be5cf authored Jan 21, 2012 by Manuel Lauss Committed by Ralf Baechle Jul 23, 2012

MIPS: Alchemy: handle db1200 cpld ints as they come in



Remove the loop in the cascade handler and instead unconditionally
handle just the first set interrupt coming from the CPLD.

This gets rid of a lot of spurious interrupts being triggered for
the SMSC91111 ethernet chip especially under high(er) IDE load:
"eth0: spurious interrupt (mask = 0xb3)"

Verified on DB1200 and DB1300.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3288/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 278bf05c

arch/mips/alchemy/devboards/bcsr.c

+1 −4

Original line number	Original line	Diff line number	Diff line
	@@ -90,10 +90,7 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
	unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);		unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);

	disable_irq_nosync(irq);		disable_irq_nosync(irq);

	for ( ; bisr; bisr &= bisr - 1)
	generic_handle_irq(bcsr_csc_base + __ffs(bisr));		generic_handle_irq(bcsr_csc_base + __ffs(bisr));

	enable_irq(irq);		enable_irq(irq);
	}		}