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Commit 697d3899 authored by Paul Mackerras's avatar Paul Mackerras Committed by Avi Kivity
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KVM: PPC: Implement MMIO emulation support for Book3S HV guests 



This provides the low-level support for MMIO emulation in Book3S HV
guests.  When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page.  Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page.  An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.

When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR.  Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.

This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
parent 06ce2c63

arch/powerpc/include/asm/kvm_book3s.h

+5 −0
Original line number Diff line number Diff line
@@ -119,6 +119,11 @@ extern void kvmppc_mmu_book3s_hv_init(struct kvm_vcpu *vcpu); 
extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte);

extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr);

extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu);

extern int kvmppc_book3s_hv_page_fault(struct kvm_run *run,

			struct kvm_vcpu *vcpu, unsigned long addr,

			unsigned long status);

extern long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr,

			unsigned long slb_v, unsigned long valid);



extern void kvmppc_mmu_hpte_cache_map(struct kvm_vcpu *vcpu, struct hpte_cache *pte);

extern struct hpte_cache *kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu);

arch/powerpc/include/asm/kvm_book3s_64.h

+26 −0
Original line number Diff line number Diff line
@@ -43,12 +43,15 @@ static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu) 
#define HPT_HASH_MASK	(HPT_NPTEG - 1)

#endif



#define VRMA_VSID	0x1ffffffUL	/* 1TB VSID reserved for VRMA */



/*

 * We use a lock bit in HPTE dword 0 to synchronize updates and

 * accesses to each HPTE, and another bit to indicate non-present

 * HPTEs.

 */

#define HPTE_V_HVLOCK	0x40UL

#define HPTE_V_ABSENT	0x20UL



static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)

{
@@ -144,6 +147,29 @@ static inline unsigned long hpte_cache_bits(unsigned long pte_val) 
#endif

}



static inline bool hpte_read_permission(unsigned long pp, unsigned long key)

{

	if (key)

		return PP_RWRX <= pp && pp <= PP_RXRX;

	return 1;

}



static inline bool hpte_write_permission(unsigned long pp, unsigned long key)

{

	if (key)

		return pp == PP_RWRW;

	return pp <= PP_RWRW;

}



static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)

{

	unsigned long skey;



	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |

		((hpte_r & HPTE_R_KEY_LO) >> 9);

	return (amr >> (62 - 2 * skey)) & 3;

}



static inline void lock_rmap(unsigned long *rmap)

{

	do {

arch/powerpc/include/asm/kvm_host.h

+5 −0
Original line number Diff line number Diff line
@@ -210,6 +210,7 @@ struct kvm_arch { 
	unsigned long lpcr;

	unsigned long rmor;

	struct kvmppc_rma_info *rma;

	unsigned long vrma_slb_v;

	int rma_setup_done;

	struct list_head spapr_tce_tables;

	spinlock_t slot_phys_lock;
@@ -452,6 +453,10 @@ struct kvm_vcpu_arch { 
#ifdef CONFIG_KVM_BOOK3S_64_HV

	struct kvm_vcpu_arch_shared shregs;



	unsigned long pgfault_addr;

	long pgfault_index;

	unsigned long pgfault_hpte[2];



	struct list_head run_list;

	struct task_struct *run_task;

	struct kvm_run *kvm_run;

arch/powerpc/include/asm/mmu-hash64.h

+1 −1
Original line number Diff line number Diff line
@@ -108,11 +108,11 @@ extern char initial_stab[]; 
#define HPTE_V_VRMA_MASK	ASM_CONST(0x4001ffffff000000)



/* Values for PP (assumes Ks=0, Kp=1) */

/* pp0 will always be 0 for linux     */

#define PP_RWXX	0	/* Supervisor read/write, User none */

#define PP_RWRX 1	/* Supervisor read/write, User read */

#define PP_RWRW 2	/* Supervisor read/write, User read/write */

#define PP_RXRX 3	/* Supervisor read,       User read */

#define PP_RXXX	(HPTE_R_PP0 | 2)	/* Supervisor read, user none */



#ifndef __ASSEMBLY__

arch/powerpc/include/asm/ppc-opcode.h

+3 −1
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
#define PPC_INST_MFSPR_DSCR_MASK	0xfc1fffff

#define PPC_INST_MTSPR_DSCR		0x7c1103a6

#define PPC_INST_MTSPR_DSCR_MASK	0xfc1fffff

#define PPC_INST_SLBFEE			0x7c0007a7



#define PPC_INST_STRING			0x7c00042a

#define PPC_INST_STRING_MASK		0xfc0007fe
@@ -183,7 +184,8 @@ 
					__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))

#define PPC_ERATSX_DOT(t, a, w)	stringify_in_c(.long PPC_INST_ERATSX_DOT | \

					__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))



#define PPC_SLBFEE_DOT(t, b)	stringify_in_c(.long PPC_INST_SLBFEE | \

					__PPC_RT(t) | __PPC_RB(b))



/*

 * Define what the VSX XX1 form instructions will look like, then add